The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. - Le Ye; Zhixuan Wang; Ying Liu 069; Peiyu Chen; Heyi Li; Hao Zhang 119; Meng Wu 005; Wei He; Linxiao Shen; Yihan Zhang 002; Zhichao Tan; Yangyuan Wang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. - Yikan Qiu; Yufei Ma 002; Wentao Zhao; Meng Wu 005; Le Ye; Ru Huang 001 (ICCAD, 2022)

Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET. - Chang Xue; Yihan Zhang 002; Peiyu Chen; Mingwei Zhu; Tianqiao Wu; Meng Wu 005; Yandong He; Le Ye (ISCAS, 2022)

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Zhixuan Wang; Wei He; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Meng Wu 005; Hao Zhang 119; Peng Zhou; Jinguang Liu; Guangyu Sun 003; Jiayoon Ru; et al. (ISSCC, 2022)

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. - Peiyu Chen; Meng Wu 005; Yufei Ma 002; Le Ye; Ru Huang 001 (ASP-DAC, 2023)

DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. - Yiqi Jing; Yiyang Sun; Xiao Wang; Wentao Zhao; Meng Wu 005; Fengyun Yan; Yufei Ma 002; Le Ye; Tianyu Jia (ISLPED, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu 069; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. - Yikan Qiu; Yufei Ma 002; Meng Wu 005; Yifan Jia 009; Xinyu Qu; Zecheng Zhou; Jincheng Lou; Tianyu Jia; Le Ye; Ru Huang 001 (CICC, 2024)

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. - Meng Wu 005; Wenjie Ren; Peiyu Chen; Wentao Zhao; Yiqi Jing; Jiayoon Ru; Zhixuan Wang; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (CICC, 2024)

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. - Zhiyuan Chen 009; Yufei Ma 002; Keyi Li; Yifan Jia 009; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (DAC, 2024)

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. - Yiqi Jing; Meng Wu 005; Jiaqi Zhou; Yiyang Sun; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (DAC, 2024)

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. - Ying Liu 069; Yufei Ma 002; Ninghui Shang; Tianhao Zhao; Peiyu Chen; Meng Wu 005; Jiayoon Ru; Tianyu Jia; Le Ye; Zhixuan Wang; Ru Huang 001 (ISSCC, 2024)

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. - Yanchi Dong; Xueping Liu; Kangbo Bai; Guoxiang Li; Meng Wu 005; Yiqi Jing; Yihan Zhang 002; Pixian Zhan; Yadong Zhang; Yufei Ma 002; Ru Huang 001; Le Ye; et al. (VLSI Technology and Circuits, 2024)

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. - Yufei Ma 002; Yikan Qiu; Wentao Zhao; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. - Zhantong Zhu; Hongou Li; Wenjie Ren; Meng Wu 005; Le Ye; Ru Huang 001; Tianyu Jia (DATE, 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)