A novel optimization algorithm for Chien search of BCH Codes in NAND flash memory devices. - Meng Zhang 014; Fei Wu 005; Changsheng Xie; You Zhou 009; Kai Zou (NAS, 2015)

REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance. - Meng Zhang 014; Fei Wu 005; Xubin He; Ping Huang 001; Shunzhuo Wang; Changsheng Xie (MSST, 2016)

Lifetime adaptive ECC in NAND flash page management. - Shunzhuo Wang; Fei Wu 005; Zhonghai Lu; You Zhou 009; Qin Xiong; Meng Zhang 014; Changsheng Xie (DATE, 2017)

FPGA-based failure mode testing and analysis for MLC NAND flash memory. - Meng Zhang 014; Fei Wu 005; He Huang; Qian Xia; Jian Zhou 004; Changsheng Xie (DATE, 2017)

CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash. - Meng Zhang 014; Fei Wu 005; Yajuan Du; Chengmo Yang; Changsheng Xie; Jiguang Wan 001 (ICCD, 2017)

Enhancing SSD performance with LDPC-aware garbage collection. - Yajuan Du; Yunpei Jia; Meng Zhang 014; Jun Zeng; Chun Jason Xue (NVMSA, 2017)

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance. - Fei Wu 005; Meng Zhang 014; Yajuan Du; Xubin He; Ping Huang 001; Changsheng Xie; Jiguang Wan 001 (ACM Trans. Embed. Comput. Syst., 2017)

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory. - Meng Zhang 014; Fei Wu 005; Xubin Chen; Yajuan Du; Weihua Liu; Yahui Zhao; Jiguang Wan 001; Changsheng Xie (IEEE Access, 2018)

Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading. - Yajuan Du; Yao Zhou; Meng Zhang 014; Wei Liu; Shengwu Xiong 001 (DAC, 2019)

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash. - Weihua Liu; Fei Wu 005; Meng Zhang 014; Yifei Wang; Zhonghai Lu; Xiangfeng Lu; Changsheng Xie (DATE, 2019)

VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash. - Lanlan Cui; Fei Wu 005; Xiaojian Liu; Meng Zhang 014; Changsheng Xie (ICCD, 2019)

United SSD block cleaning via constrained victim block selection. - Yajuan Du; Wei Liu; Yu Zhu; Meng Zhang 014 (SAC, 2019)

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory. - Ruixiang Ma; Fei Wu 005; Meng Zhang 014; Zhonghai Lu; Jiguang Wan 001; Changsheng Xie (IEEE Access, 2019)

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory. - Meng Zhang 014; Fei Wu 005; Yajuan Du; Weihua Liu; Changsheng Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. - Meng Zhang 014; Fei Wu 005; Qin Yu; Weihua Liu; Lanlan Cui; Yahui Zhao; Changsheng Xie (DATE, 2020)

Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions. - Yachen Kong; Meng Zhang 014; Xuepeng Zhan; Rui Cao; Jiezhi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash. - Fei Wu 005; Meng Zhang 014; Yajuan Du; Weihua Liu; Zuo Lu; Jiguang Wan 001; Zhi-hu Tan; Changsheng Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory. - Weihua Liu; Fei Wu 005; Jian Zhou 004; Meng Zhang 014; Chengmo Yang; Zhonghai Lu; Yu Wang 168; Changsheng Xie (DATE, 2021)

Write-Optimized B+ Tree Index Technology for Persistent Memory. - Ruixiang Ma; Fei Wu 005; Bu-Rong Dong; Meng Zhang 014; Wei-Jun Li; Changsheng Xie (J. Comput. Sci. Technol., 2021)

DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD. - Weihua Liu; Fei Wu 005; Meng Zhang 014; Chengmo Yang; Zhonghai Lu; Jiguang Wan 001; Changsheng Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Work-in-Progress: High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage. - Xiaotong Fang; Meng Zhang 014; Yifan Guo; Fei Chen; Binglu Chen; Xuepeng Zhan; Jixuan Wu; Fei Wu 005; Jiezhi Chen (CASES, 2022)

Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory. - Menghua Jia; Yachen Kong; Xuepeng Zhan; Meng Zhang 014; Fei Wu 005; Jiezhi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision. - Lanlan Cui; Fei Wu 005; Xiaojian Liu; Meng Zhang 014; Renzhi Xiao; Changsheng Xie (ACM Trans. Design Autom. Electr. Syst., 2022)

Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory. - Weihua Liu; Fei Wu 005; Xiang Chen; Meng Zhang 014; Yu Wang 168; Xiangfeng Lu; Changsheng Xie (ACM Trans. Storage, 2022)

ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER Variation. - Meng Zhang 014; Xiaoyi Zhang; Fei Wu 005; Kai Tao; Feng Zhu 024; Shu Li; Yahui Zhao; Changsheng Xie (IEEE Trans. Consumer Electron., 2023)

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory. - Yingge Li; Guojun Han; Sanwei Huang; Chang Liu 008; Meng Zhang 014; Fei Wu 005 (IEEE Trans. Consumer Electron., 2023)

eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory. - Meng Zhang 014; Fei Wu 005; Qin Yu; Neidong Fu; Changsheng Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage. - Xiaotong Fang; Meng Zhang 014; Yifan Guo; Fei Chen; Binglu Chen; Xuepeng Zhan; Jixuan Wu; Fei Wu 005; Jiezhi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D nand Flash Memory. - Yingge Li; Guojun Han; Chang Liu 008; Meng Zhang 014; Fei Wu 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory. - Lanlan Cui; Meng Zhang 014; Fei Wu 005 (ICCD, 2024)

Improving DRAM Reliability Using a High Order Error Correction Code. - Wei Li; Meng Zhang 014; Tianwei Gui; Zheng Fang; Changsheng Xie; Fei Wu 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling. - Guangkuo Yang; Meng Zhang 014; Peng Guo; Xuepeng Zhan; Shaoqi Yang; Xiaohuan Zhao; Xinyi Guo; Pengpeng Sang; Jixuan Wu; Fei Wu 005; Jiezhi Chen (IEEE Trans. Computers, 2025)

Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling. - Shaoqi Yang; Meng Zhang 014; Xuepeng Zhan; Peng Guo; Xiaohuan Zhao; Guangkuo Yang; Xinyi Guo; Jixuan Wu; Fei Wu 005; Jiezhi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)