FACRA: Flexible-Core Architecture Chip Resource Abstractor. - Tao Sun; Hong An; Yongqing Ren; Mengjie Mao; Yang Liu; Mu Xu; Qi Li 034 (PDCAT, 2010)

Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor. - Bobin Deng; Hong An; Qi Li 034; Gongming Li; Mengjie Mao (ACIS-ICIS, 2012)

Distributed Control Independence for Composable Multi-processors. - Mengjie Mao; Hong An; Tao Sun; Qi Li 034; Bobin Deng; Xuechao Wei; Junrui Zhou (ACIS-ICIS, 2012)

Distributed replay protocol for distributed uniprocessors. - Mengjie Mao; Hong An; Bobin Deng; Tao Sun; Xuechao Wei; Wei Zhou; Wenting Han (ICS, 2012)

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. - Mengjie Mao; Hai (Helen) Li; Alex K. Jones; Yiran Chen 001 (ACM Great Lakes Symposium on VLSI, 2013)

Unleashing the potential of MLC STT-RAM caches. - Xiuyuan Bi; Mengjie Mao; Danghui Wang; Hai Li 001 (ICCAD, 2013)

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. - Wujie Wen; Mengjie Mao; Xiaochun Zhu; Seung-Hyuk Kang; Danghui Wang; Yiran Chen 001 (ICCAD, 2013)

Prefetching techniques for STT-RAM based last-level cache in CMP systems. - Mengjie Mao; Guangyu Sun 003; Yong Li 009; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. - Mengjie Mao; Wujie Wen; Yaojun Zhang; Yiran Chen 001; Hai (Helen) Li (DAC, 2014)

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. - Wujie Wen; Yaojun Zhang; Mengjie Mao; Yiran Chen 001 (DAC, 2014)

A heterogeneous computing system with memristor-based neuromorphic accelerators. - Xiaoxiao Liu 001; Mengjie Mao; Hai Li 001; Yiran Chen 001; Hao Jiang 014; J. Joshua Yang; Qing Wu 002; Mark Barnell (HPEC, 2014)

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). - Hai Li 001; Xiaoxiao Liu 001; Mengjie Mao; Yiran Chen 001; Qing Wu 002; Mark Barnell (ISIC, 2014)

Emerging memristor technology enabled next generation cortical processor. - Hai Li 001; Miao Hu 002; Xiaoxiao Liu 001; Mengjie Mao; Chuandong Li 001; Shukai Duan 001 (SoCC, 2014)

An efficient STT-RAM-based register file in GPU architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Li 001; Yiran Chen 001 (ASP-DAC, 2015)

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. - Xiaoxiao Liu 001; Mengjie Mao; Beiye Liu; Hai Li 001; Yiran Chen 001; Boxun Li; Yu Wang 002; Hao Jiang 014; Mark Barnell; Qing Wu 002; Jianhua Joshua Yang (DAC, 2015)

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications. - Mengjie Mao; Jingtong Hu; Yiran Chen 001; Hai Li 001 (DAC, 2015)

The applications of memristor devices in next-generation cortical processor designs. - Hai Li 001; Beiye Liu; Xiaoxiao Liu 001; Mengjie Mao; Yiran Chen 001; Qing Wu 002; Qinru Qiu (ISCAS, 2015)

TEMP: thread batch enabled memory partitioning for GPU. - Mengjie Mao; Wujie Wen; Xiaoxiao Liu 001; Jingtong Hu; Danghui Wang; Yiran Chen 001; Hai Li 001 (DAC, 2016)

Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache. - Xue Wang; Mengjie Mao; Enes Eken; Wujie Wen; Hai Li 001; Yiran Chen 001 (DATE, 2016)

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations. - Wujie Wen; Mengjie Mao; Hai Li 001; Yiran Chen 001; Yukui Pei; Ning Ge 001 (DATE, 2016)

Heterogeneous systems with reconfigurable neuromorphic computing accelerators. - Sicheng Li 001; Xiaoxiao Liu 001; Mengjie Mao; Hai (Helen) Li; Yiran Chen 001; Boxun Li; Yu Wang 002 (ISCAS, 2016)

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. - Xiaoxiao Liu 001; Mengjie Mao; Beiye Liu; Boxun Li; Yu Wang 002; Hao Jiang 014; Mark Barnell; Qing Wu 002; Jianhua Joshua Yang; Hai Li 001; Yiran Chen 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. - Mengjie Mao; Wujie Wen; Yaojun Zhang; Yiran Chen 001; Hai Li 001 (IEEE Trans. Computers, 2017)

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. - Xiuyuan Bi; Mengjie Mao; Danghui Wang; Hai Helen Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. - Zihao Liu; Mengjie Mao; Tao Liu 023; Xue Wang; Wujie Wen; Yiran Chen 001; Hai Li 001; Danghui Wang; Yukui Pei; Ning Ge 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Thread Batching for High-performance Energy-efficient GPU Memory Design. - Bing Li 017; Mengjie Mao; Xiaoxiao Liu 001; Tao Liu 023; Zihao Liu; Wujie Wen; Yiran Chen 001; Hai (Helen) Li (ACM J. Emerg. Technol. Comput. Syst., 2019)

Exploring Applications of STT-RAM in GPU Architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Helen Li; Yiran Chen 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)