Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. - Menglin Han; Hao Cai 001; Jun Yang 006; Lirida A. B. Naviner; You Wang 002; Weisheng Zhao (APCCAS, 2018)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (DCIS, 2018)

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. - Hao Cai 001; Menglin Han; Weiwei Shan; Jun Yang 006; You Wang 002; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2019)

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. - Hao Cai 001; Honglan Jiang; Menglin Han; Zhaohao Wang; You Wang 002; Jun Yang 006; Jie Han 001; Leibo Liu; Weisheng Zhao (ISVLSI, 2019)

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. - Mingyue Liu; Hao Cai 001; Menglin Han; Lei Xie; Jun Yang 006; Lirida A. B. Naviner (NANOARCH, 2019)

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. - Yongliang Zhou; Menglin Han; Mingyue Liu; Hao Cai 001; Bo Liu 019; Jun Yang 006 (NANOARCH, 2019)

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. - Hao Cai 001; Honglan Jiang; Yongliang Zhou; Menglin Han; Bo Liu 019 (CCF Trans. High Perform. Comput., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)