Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. - Menka Yadav; Anand Bulusu; Sudeb Dasgupta (Microelectron. J., 2013)

Performance Assessment of Dual Metal Graded Channel Negative Capacitance Junctionless FET for Digital/Analog field. - Shalini Chaudhary; Basudha Dewan; Chitrakant Sahu; Menka Yadav (iSES, 2021)

Smart Attendance Cum Health Check Up Machine For Students. - Pranjal Patel; Shriram Sharma; Pritesh Sutrakar; Hemant Kumar; Devender Pal Singh; Menka Yadav (iSES, 2021)

Performance Analysis of Junctionless and Inversion Mode Trigate SOI FinFET at 20nm Gate Length. - Devender Pal Singh; Menka Yadav (iSES, 2022)

Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/ RF applications. - Shalini Chaudhary; Basudha Dewan; Chitrakant Sahu; Menka Yadav (Microelectron. J., 2022)

A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell. - Devender Pal Singh; Priyanka Yadav; Menka Yadav (iSES, 2023)

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects. - Rashi Chaudhary; Rajesh Saha; Menka Yadav (Microelectron. J., 2024)

Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET. - Devender Pal Singh; Shalini Chaudhary; Basudha Dewan; Menka Yadav (Microelectron. J., 2024)