iPRIDE: a parallel integrated circuit simulator using direct method. - Mi-Chang Chang; Ibrahim N. Hajj (ICCAD, 1988)

Efficient direct-method parallel circuit simulation using multilevel node tearing - Mi-Chang Chang (1989)

An accurate grid local truncation error for device simulation. - Mi-Chang Chang; Jue-Hsien Chern; Ping Yang 001 (ICCAD, 1993)

Efficient and Robust Path Tracing Algorithm for DC Convergence Problem. - Mi-Chang Chang; Jue-Hsien Chern; Ping Yang 001 (ISCAS, 1993)

High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies. - Chung-Hui Chen; Yean-Kuen Fang; Chien-Chun Tsai; Shen Tu; Mark K. L. Chen; Mi-Chang Chang (CICC, 2002)

Application-dependent scaling tradeoffs and optimization in the SoC era. - Carlos H. Diaz; Mi-Chang Chang; Tong-Chern Ong; Jack Yuan-Chen Sun (CICC, 2002)

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. - Carlos H. Diaz; Mi-Chang Chang; Tong-Chern Ong; Jack Yuan-Chen Sun (IEEE J. Solid State Circuits, 2003)

Device trends and implications on circuit design in advanced CMOS technologies. - Carlos H. Diaz; K. H. Fung; Ying-Keung Leung; Chung-Cheng Wu; Chih-Ping Chao; G. J. Chern; Wesley L. Lin; Chien-Ming Lee; Fang-Shi Lai; Mi-Chang Chang; Yuan-Chen Sun (CICC, 2005)

An Automatic Layout Generator for I/O Cells. - Li-Chun Tien; Jing-Jou Tang; Mi-Chang Chang (IWSOC, 2005)

Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process. - Hung-Wei Chen; Mi-Chang Chang (Microelectron. Reliab., 2017)

Improving ESD protection of 5V NMOSFET large array device in 0.4μm BCD process. - Shao-Chang Huang; Hung-Wei Chen; Jen-Hang Yang; Mi-Chang Chang (Microelectron. Reliab., 2018)