Decimal Multiplication Using Combination of Software and Hardware. - Mian Riaz-ul-haque; Michihiro Shintani; Michiko Inoue (APCCAS, 2018)

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. - Riaz-ul-haque Mian; Michihiro Shintani; Michiko Inoue (SoCC, 2019)

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. - Michihiro Shintani; Riaz-ul-haque Mian; Michiko Inoue; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki (ITC, 2021)

Hardware-Software Co-Design for Decimal Multiplication. - Riaz-ul-haque Mian; Michihiro Shintani; Michiko Inoue (Comput., 2021)

Hierarchical Active Learning for Efficient Semi-Supervised Seagrass Image Classification. - Farah Afifah Binti Mohd Nawayai; Md Kislu Noman; Syed Mohammed Shamsul Islam; Riaz-ul-haque Mian (DICTA, 2024)

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. - Riaz-ul-haque Mian; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki; Michihiro Shintani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Approach to Visual Attractiveness of Event Space Through Data-Driven Environment and Spatial Perception. - Aliffi Majiid; Riaz-ul-haque Mian; Kouki Kurohara; Yen-Khang Nguyen-Tran (CoRR, 2025)

Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning. - Wang WeiQuan; Riaz-ul-haque Mian (CoRR, 2025)

Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis. - Riaz-ul-haque Mian; Foisal Ahmed; Yoshito Hagihara; Souma Yamane (J. Electron. Test., 2025)