PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems. - Miao-Shan Li; Yen-Kuei Lu; Ching-Yuan Yang; Chin-Lung Lin (ISOCC, 2019)

A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. - You-Sheng Lin; Miao-Shan Li; Ching-Yuan Yang (SoCC, 2019)

A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. - Yen-Kuei Lu; Miao-Shan Li; Ching-Yuan Yang; Chin-Lung Lin (A-SSCC, 2021)

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. - Ching-Yuan Yang; Miao-Shan Li; Ai-Jia Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2021)