A SPICE model for a novel brushless adjustable-speed drive. - Michael A. Inerfield; Steven L. Garverick; Wyatt S. Newman; Yuandao Zhang (IEEE Trans. Ind. Electron., 2000)

A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS. - Sandeep Gupta; Michael Choi; Michael A. Inerfield; Jingbo Wang (ISSCC, 2006)

A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture. - Sandeep K. Gupta 003; Michael A. Inerfield; Jingbo Wang (IEEE J. Solid State Circuits, 2006)

A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS. - Sandeep Gupta; José Tellado; Sridhar Begur; Frank Yang; Vishnu Balan; Michael A. Inerfield; Dariush Dabiri; John Dring; Sachin Goel; Kumaraguru Muthukumaraswamy; Frank McCarthy; Glenn Golden; et al. (ISSCC, 2008)

A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-Chip. - Xicheng Jiang; Xinyu Yu; Fang Lin; Felix Cheung; Mike Inerfield; Kevin Li; Abhishek Kamath; Harsh Mehta; Jingbo Duan; Jing Yang; Gautham Krishnamurthy; Sumant Ranganathan; et al. (ESSCIRC, 2014)

An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS. - Michael A. Inerfield; Abhishek Kamath; Feng Su; Jason Hu; Xinyu Yu; Victor Fong; Omar Alnaggar; Fang Lin; Tom Kwan (VLSIC, 2014)

A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS. - Harsh Mehta; Gautham Krishnamurthy; Michael A. Inerfield; Fang Lin; Tom Kwan (VLSIC, 2014)