A framework for scheduling parallel dbms user-defined programs on an attached high-performance computer. - Michael A. Kochte; Ramesh Natarajan (Conf. Computing Frontiers, 2008)

Test Set Stripping Limiting the Maximum Number of Specified Bits. - Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Hans-Joachim Wunderlich (DELTA, 2008)

Test exploration and validation using transaction level models. - Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo; Paolo Prinetto (DATE, 2009)

Test Encoding for Extreme Response Compaction. - Michael A. Kochte; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2009)

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. - Michael A. Kochte; Christian G. Zoellin; Hans-Joachim Wunderlich (ETS, 2009)

On Determining the Real Output Xs by SAT-Based Reasoning. - Melanie Elm; Michael A. Kochte; Hans-Joachim Wunderlich (Asian Test Symposium, 2010)

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. - Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo; Paolo Prinetto (Asian Test Symposium, 2010)

Efficient fault simulation on many-core processors. - Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich; Christian G. Zoellin (DAC, 2010)

System reliability evaluation using concurrent multi-level simulation of structural faults. - Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo; Paolo Prinetto (ITC, 2010)

Efficient Concurrent Self-Test with Partially Specified Patterns. - Michael A. Kochte; Christian G. Zoellin; Hans-Joachim Wunderlich (J. Electron. Test., 2010)

Efficient BDD-based Fault Simulation in Presence of Unknown Values. - Michael A. Kochte; Sandip Kundu; Kohei Miyase; Xiaoqing Wen; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

SAT-based fault coverage evaluation in the presence of unknown values. - Michael A. Kochte; Hans-Joachim Wunderlich (DATE, 2011)

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. - Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto; Hans-Joachim Wunderlich (ISLPED, 2011)

A novel scan segmentation design method for avoiding shift timing failure in scan testing. - Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara; Laung-Terng Wang (ITC, 2011)

Power-aware test generation with guaranteed launch safety for at-speed scan testing. - Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard 001; Mohammad Tehranipoor (VTS, 2011)

Efficient multi-level fault simulation of HW/SW systems for structural faults. - Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich; Christian G. Zoellin (Sci. China Inf. Sci., 2011)

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Hans-Joachim Wunderlich; Jörg Henkel (AHS, 2012)

Exact stuck-at fault classification in presence of unknowns. - Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich; Bernd Becker 001 (ETS, 2012)

Transparent structural online test for reconfigurable systems. - Mohamed Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IOLTS, 2012)

Modeling, verification and pattern generation for reconfigurable scan networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ITC, 2012)

Accurate X-Propagation for Test Applications by SAT-Based Reasoning. - Michael A. Kochte; Melanie Elm; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Securing Access to Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (Asian Test Symposium, 2013)

Accurate Multi-cycle ATPG in Presence of X-Values. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (Asian Test Symposium, 2013)

Accurate QBF-based test pattern generation in presence of unknown values. - Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich; Bernd Becker 001 (DATE, 2013)

SAT-based code synthesis for fault-secure circuits. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (DFTS, 2013)

Scan pattern retargeting and merging with reduced access time. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ETS, 2013)

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich; Jörg Henkel (ITC, 2013)

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. - Yuta Yamato; Kohei Miyase; Seiji Kajihara; Xiaoqing Wen; Laung-Terng Wang; Michael A. Kochte (IEEE Des. Test, 2013)

Test Strategies for Reliable Runtime Reconfigurable Architectures. - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IEEE Trans. Computers, 2013)

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. - Hongyan Zhang 004; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (DAC, 2014)

Area-efficient synthesis of fault-secure NoC switches. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2014)

Test pattern generation in presence of unknown values based on restricted symbolic logic. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ITC, 2014)

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. - Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Hans-Joachim Wunderlich (ITC, 2014)

Verifikation Rekonfigurierbarer Scan-Netze. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (MBMV, 2014)

Access Port Protection for Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

Exact Logic and Fault Simulation in Presence of Unknowns. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Stefan Hillebrecht; Tobias Schubert 001; Hans-Joachim Wunderlich; Bernd Becker 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Boolean reasoning for digital circuits in presence of unknown values: application to test automation. - Michael A. Kochte (2014)

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. - Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jun Qian (ATS, 2015)

Optimized Selection of Frequencies for Faster-Than-at-Speed Test. - Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2015)

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. - Michael A. Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omaña 001; Cecilia Metra; Hans-Joachim Wunderlich (ATS, 2015)

GPU-accelerated small delay fault simulation. - Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (DATE, 2015)

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (DFTS, 2015)

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (ICCAD, 2015)

Efficient observation point selection for aging monitoring. - Chang Liu 010; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2015)

Efficient on-line fault-tolerance for the preconditioned conjugate gradient method. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2015)

Adaptive multi-layer techniques for increased system dependability. - Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes Maximilian Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich; Hongyan Zhang 004 (it Inf. Technol., 2015)

Fine-Grained Access Management in Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. - Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2015)

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ASP-DAC, 2016)

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. - Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich; Michael A. Kochte (ATS, 2016)

Test Strategies for Reconfigurable Scan Networks. - Michael A. Kochte; Rafal Baranowski; Marcel Schaal; Hans-Joachim Wunderlich (ATS, 2016)

Autonomous Testing for 3D-ICs with IEEE Std. 1687. - Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee; Hans-Joachim Wunderlich (ATS, 2016)

Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (DSN, 2016)

Formal verification of secure reconfigurable scan network infrastructure. - Michael A. Kochte; Rafal Baranowski; Matthias Sauer 002; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2016)

An on-chip self-test architecture with test patterns recorded in scan chains. - Kuen-Jong Lee; Pin-Hao Tang; Michael A. Kochte (ITC, 2016)

Dependable on-chip infrastructure for dependable MPSOCs. - Michael A. Kochte; Hans-Joachim Wunderlich (LATS, 2016)

Structure-Oriented Test of Reconfigurable Scan Networks. - Dominik Ull; Michael A. Kochte; Hans-Joachim Wunderlich (ATS, 2017)

Specification and verification of security in reconfigurable scan networks. - Michael A. Kochte; Matthias Sauer 002; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2017)

Trustworthy reconfigurable access to on-chip infrastructure. - Michael A. Kochte; Rafal Baranowski; Hans-Joachim Wunderlich (ITC-Asia, 2017)

Analysis and mitigation or IR-Drop induced scan shift-errors. - Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara; Xiaoqing Wen (ITC, 2017)

Aging monitor reuse for small delay fault testing. - Chang Liu 010; Michael A. Kochte; Hans-Joachim Wunderlich (VTS, 2017)

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jörg Henkel (IEEE Trans. Computers, 2017)

Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. - Wen-Hsuan Hsu; Michael Andreas Kochte; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

GPU-Accelerated Simulation of Small Delay Faults. - Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Multi-level timing simulation on GPUs. - Eric Schneider; Michael A. Kochte; Hans-Joachim Wunderlich (ASP-DAC, 2018)

Online prevention of security violations in reconfigurable scan networks. - Ahmed Atteya; Michael A. Kochte; Matthias Sauer 002; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2018)

Detecting and Resolving Security Violations in Reconfigurable Scan Networks. - Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (IOLTS, 2018)

Self-Test and Diagnosis for Self-Aware Systems. - Michael A. Kochte; Hans-Joachim Wunderlich (IEEE Des. Test, 2018)

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. - Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (ITC, 2019)

Built-In Test for Hidden Delay Faults. - Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Eric Schneider; Sybille Hellebrand; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. - Kuen-Jong Lee; Bo-Ren Chen; Michael Andreas Kochte (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Synthesis of Fault-Tolerant Reconfigurable Scan Networks. - Sebastian Brandhofer; Michael A. Kochte; Hans-Joachim Wunderlich (DATE, 2020)