A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. - Alexander V. Rylyakov; José A. Tierno; George English; Michael A. Sperling; Daniel J. Friedman (CICC, 2008)

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; William R. Reohr; Kavita Nair; Nianzheng Cao (ISSCC, 2010)

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; Toshiaki Kirihata; William R. Reohr; Kavita Nair; Nianzheng Cao (IEEE J. Solid State Circuits, 2011)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; Timothy E. Diemoz; John F. Bulzacchelli; Zeynep Toprak Deniz (CICC, 2019)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; John F. Bulzacchelli; Zeynep Toprak Deniz; Timothy E. Diemoz (IEEE J. Solid State Circuits, 2020)

2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator. - Gerald Strevig; Christopher J. Berry; Rahul M. Rao; Noam Jungmann; Michael A. Sperling; Michael J. Becht; Eduard Herkel; Matthias Pflanz; Patrick J. Meaney; Michael Romain; Mark Cichanowski; Amanda Venton; et al. (ISSCC, 2025)