High-performance low-power AND and Sense-Amp address decoders with selective precharging. - Michael A. Turi; José G. Delgado-Frias (ISCAS, 2008)

High-Performance Low-Power Selective Precharge Schemes for Address Decoders. - Michael A. Turi; José G. Delgado-Frias (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Decreasing energy consumption in address decoders by means of selective precharge schemes. - Michael A. Turi; José G. Delgado-Frias (Microelectron. J., 2009)

Low power SRAM cell design for FinFET and CNTFET technologies. - José G. Delgado-Frias; Zhe Zhang; Michael A. Turi (Green Computing Conference, 2010)

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. - Zhe Zhang; Michael A. Turi; José G. Delgado-Frias (ACM Great Lakes Symposium on VLSI, 2012)

FinFET 3T and 3T1D dynamic RAM cells. - Colby M. Gerik; Michael A. Turi; José G. Delgado-Frias (MWSCAS, 2012)

An evaluation of 6T and 8T FinFET SRAM cell leakage currents. - Michael A. Turi; José G. Delgado-Frias (MWSCAS, 2014)

Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. - José G. Delgado-Frias; Zhe Zhang; Michael A. Turi (ISCAS, 2015)

SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells. - Ahmed S. Sajit; Michael A. Turi (CCWC, 2017)

An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice. - Michael A. Turi; José G. Delgado-Frias (CCWC, 2017)

Full-VDD and near-threshold performance of 8T FinFET SRAM cells. - Michael A. Turi; José G. Delgado-Frias (Integr., 2017)

Scripts for Easier Use of Spice (SEUS): A Perl script package for simulating and creating batches of circuit netlists for Monte Carlo simulations when using Ngspice or Ngspice-based simulators. - Michael A. Turi (J. Open Source Softw., 2020)

Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. - Michael A. Turi; José G. Delgado-Frias (IEEE Trans. Circuits Syst. II Express Briefs, 2020)