A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. - Tsung-Kai Kao; Che-Fu Liang; Hsien-Hsiang Chiu; Michael Ashburn (ISSCC, 2013)

An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency. - Patrick Riehl; Paul Fowers; Hao-Ping Hong; Michael Ashburn (ISSCC, 2013)

28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS. - Sheng-Jui Huang; Nathan Egan; Divya Kesharwani; Frank Opteynde; Michael Ashburn (ISSCC, 2017)

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. - Tao He 001; Michael Ashburn; Stacy Ho; Yi Zhang 023; Gabor C. Temes (ISSCC, 2018)

A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD. - Ayman Shabra; Padraig Cooney; Adalberto Cantoni; Joshua Bamford; Stacy Ho; Michael Ashburn (CICC, 2019)