Placement for configurable dataflow architecture. - Mongkol Ekpanyapong; Michael B. Healy; Sung Kyu Lim (ASP-DAC, 2005)

MILP-based Placement and Routing for Dataflow Architecture. - Michael B. Healy; Mongkol Ekpanyapong; Sung Kyu Lim (FPL, 2005)

Microarchitectural floorplanning under performance and thermal tradeoff. - Michael B. Healy; Mario Vittes; Mongkol Ekpanyapong; Chinnakrishnan S. Ballapuram; Sung Kyu Lim; Hsien-Hsin S. Lee; Gabriel H. Loh (DATE, 2006)

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. - Fayez Mohamood; Michael B. Healy; Sung Kyu Lim; Hsien-Hsin S. Lee (MICRO, 2006)

Profile-Driven Instruction Mapping for Dataflow Architectures. - Mongkol Ekpanyapong; Michael B. Healy; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. - Fayez Mohamood; Michael B. Healy; Sung Kyu Lim; Hsien-Hsin S. Lee (ASP-DAC, 2007)

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. - Michael B. Healy; Mario Vittes; Mongkol Ekpanyapong; Chinnakrishnan S. Ballapuram; Sung Kyu Lim; Hsien-Hsin S. Lee; Gabriel H. Loh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A unified methodology for power supply noise reduction in modern microarchitecture design. - Michael B. Healy; Fayez Mohamood; Hsien-Hsin S. Lee; Sung Kyu Lim (ASP-DAC, 2008)

Thermal optimization in multi-granularity multi-core floorplanning. - Michael B. Healy; Hsien-Hsin S. Lee; Gabriel H. Loh; Sung Kyu Lim (ASP-DAC, 2009)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

A novel TSV topology for many-tier 3D power-delivery networks. - Michael B. Healy; Sung Kyu Lim (DATE, 2011)

Power-supply-network design in 3D integrated systems. - Michael B. Healy; Sung Kyu Lim (ISQED, 2011)

Floorplanning challenges in early chip planning. - Jeonghee Shin; John A. Darringer; Guojie Luo; Merav Aharoni; Alexey Lvov; Gi-Joon Nam; Michael B. Healy (SoCC, 2011)

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. - Michael B. Healy; Fayez Mohamood; Hsien-Hsin S. Lee; Sung Kyu Lim (ACM Trans. Design Autom. Electr. Syst., 2011)

Power management of multi-core chips: Challenges and pitfalls. - Pradip Bose; Alper Buyuktosunoglu; John A. Darringer; Meeta Sharma Gupta; Michael B. Healy; Hans M. Jacobson; Indira Nair; Jude A. Rivers; Jeonghee Shin; Augusto Vega; Alan J. Weger (DATE, 2012)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

Distributed TSV Topology for 3-D Power-Supply Networks. - Michael B. Healy; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

3D stacking of high-performance processors. - Philip G. Emma; Alper Buyuktosunoglu; Michael B. Healy; Krishnan Kailas; Valentin Puente; Roy Yu; Allan Hartstein; Pradip Bose; Jaime H. Moreno; Eren Kursun (HPCA, 2014)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)

CramSim: controller and memory simulator. - Michael B. Healy; Seokin Hong (MEMSYS, 2017)

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. - Seokin Hong; Prashant Jayaprakash Nair; Bülent Abali; Alper Buyuktosunoglu; Kyu-Hyoun Kim; Michael B. Healy (MICRO, 2018)

Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. - Ben Lin; Michael B. Healy; Rustam Miftakhutdinov; Philip G. Emma; Yale N. Patt (MICRO, 2018)

Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. - Seokin Hong; Bülent Abali; Alper Buyuktosunoglu; Michael B. Healy; Prashant J. Nair (MICRO, 2019)

Design and Architecture of the IBM Quantum Engine Compiler. - Michael B. Healy; Reza Jokar; Soolu Thomas; Vincent R. Pascuzzi; Kit Barton; Thomas A. Alexander; Roy Elkabetz; Brian C. Donovan; Hiroshi Horii; Marius Hillenbrand (QCE, 2024)