Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. - Michael Buttrick; Sandip Kundu (ISVLSI, 2011)

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. - Michael Buttrick; Sandip Kundu (J. Electron. Test., 2012)