A high performance dielectric measurement system. - Michael Christian Wohnsen Coln (1985)

"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. - John A. McNeill; Michael C. W. Coln; Brian J. Larivee (IEEE J. Solid State Circuits, 2005)

Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC". - Jipeng Li; Un-Ku Moon; John A. McNeill; Michael C. W. Coln; Brian J. Larivee (IEEE J. Solid State Circuits, 2006)

Digital Background-Calibration Algorithm for "Split ADC" Architecture. - John A. McNeill; Michael C. W. Coln; D. Richard Brown; Brian J. Larivee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors. - John A. McNeill; Christopher L. David; Michael C. W. Coln; Rosa Croughwell (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

All-Digital Background Calibration of a Successive Approximation ADC Using the "Split ADC" Architecture. - John A. McNeill; Ka Yan Chan; Michael C. W. Coln; Christopher L. David; Cody Brenneman (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS. - John A. McNeill; Christopher L. David; Michael C. W. Coln; Ka Yan Chan; Cody Brenneman (I2MTC, 2013)

A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability. - Roddy C. McLachlan; Alan Gillespie; Michael C. W. Coln; Douglas Chisholm; Denise T. Lee (ISSCC, 2013)

A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability. - Roddy C. McLachlan; Alan Gillespie; Michael C. W. Coln; Douglas Chisholm; Denise T. Lee (IEEE J. Solid State Circuits, 2013)

A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS. - Mark Maddox; Baozhen Chen; Michael C. W. Coln; Ron Kapusta; Junhua Shen; Lalinda Fernando (A-SSCC, 2016)

A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL. - Hongxing Li; Mark Maddox; Michael C. W. Coln; William Buckley; Derek Hummerston; Naveed Naeem (ISSCC, 2018)

Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results. - Baozhen Chen; Mark Maddox; Michael C. W. Coln; Ye Lu; Junhua Shen; Lalinda Fernando (IEEE J. Solid State Circuits, 2018)

Corrections to "Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results". - Baozhen Chen; Mark Maddox; Michael C. W. Coln; Ye Lu; Junhua Shen; Lalinda D. Fernando (IEEE J. Solid State Circuits, 2018)

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS. - Junhua Shen; Akira Shikata; Lalinda Fernando; Ned Guthrie; Baozhen Chen; Mark Maddox; Nikhil Mascarenhas; Ron Kapusta; Michael C. W. Coln (IEEE J. Solid State Circuits, 2018)

A 1-V 560-nW SAR ADC With 90-dB SNDR for IoT Sensing Applications. - Huajun Zhang 001; Zhichao Tan; Chao Chu; Baozhen Chen; Hongxing Li; Michael C. W. Coln; Khiem Nguyen (IEEE Trans. Circuits Syst. II Express Briefs, 2019)