A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. - Dirk Reese; Eric Chun; Sammy Cheung; Edmond Lau; Michael Chu; Gwen Liang; Nghia Van Tran; Brad Vest; Richard Smolen; Minchang Liang; Seshan Sekariapuram; Behzad Nouban; et al. (CICC, 1998)

Object Oriented Circuit-Generators in Java. - Michael Chu; Nicholas Weaver; Kolja Sulimma; André DeHon; John Wawrzynek (FCCM, 1998)

DataSplash. - Chris Olston; Allison Woodruff; Alexander Aiken; Michael Chu; Vuk Ercegovac; Mark Lin; Mybrid Spalding; Michael Stonebraker (SIGMOD Conference, 1998)

Stream Computations Organized for Reconfigurable Execution (SCORE). - Eylon Caspi; Michael Chu; Randy Huang; Joseph Yeh; John Wawrzynek; André DeHon (FPL, 2000)

DataSplash: A Direct Manipulation Environment for Programming Semantic Zoom Visualizations of Tabular Data. - Allison Woodruff; Chris Olston; Alexander Aiken; Michael Chu; Vuk Ercegovac; Mark Lin; Mybrid Spalding; Michael Stonebraker (J. Vis. Lang. Comput., 2001)

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. - Yury Markovsky; Eylon Caspi; Randy Huang; Joseph Yeh; Michael Chu; John Wawrzynek; André DeHon (FPGA, 2002)

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes. - Kuan Zhou; Channakeshav; Michael Chu; Jong-Ru Guo; S.-C. Liu; Russell P. Kraft; Chao You; John F. McDonald 001 (FPT, 2002)

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. - Jong-Ru Guo; Chao You; Michael Chu; Kuan Zhou; Young Uk Yim; Robert W. Heikaus; Russell P. Kraft; John F. McDonald 001 (Engineering of Reconfigurable Systems and Algorithms, 2003)

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. - Kuan Zhou; Michael Chu; Chao You; Jong-Ru Guo; Channakeshav; John Mayega; John F. McDonald 001; Russell P. Kraft; Bryan S. Goda (FPGA, 2003)

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Robert W. Heikaus; Okan Erdogan; Peter F. Curran; Bryan S. Goda; Kuan Zhou; John F. McDonald 001 (FPL, 2003)

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. - Chao You; Jong-Ru Guo; Russell P. Kraft; Kuan Zhou; Michael Chu; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2003)

The gigahertz FPGA: design consideration and applications. - Jong-Ru Guo; Chao You; Michael Chu; Robert W. Heikaus; Kuan Zhou; Okan Erdogan; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPGA, 2004)

The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. - Jong-Ru Guo; Chao You; Peter F. Curran; Michael Chu; Kuan Zhou; Jiedong Diao; A. George; Russell P. Kraft; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2004)

A 11 GHz FPGA with Test Applications. - Chao You; Jong-Ru Guo; Michael Chu; Russell P. Kraft; Bryan S. Goda; John F. McDonald 001 (FPL, 2005)

A High Speed Reconfigurable Gate Array for Gigahertz Applications. - Jong-Ru Guo; Chao You; Michael Chu; Okan Erdogan; Russell P. Kraft; John F. McDonald 001 (ISVLSI, 2005)

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. - Jong-Ru Guo; Chao You; Kuan Zhou; Michael Chu; Peter F. Curran; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (Integr., 2005)

A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Peter F. Curran; Kuan Zhou; Bryan S. Goda; John F. McDonald 001 (Microprocess. Microsystems, 2005)

Hybrid transactional memory. - Sanjeev Kumar; Michael Chu; Christopher J. Hughes; Partha Kundu; Anthony D. Nguyen (PPoPP, 2006)

Stream computations organized for reconfigurable execution. - André DeHon; Yury Markovsky; Eylon Caspi; Michael Chu; Randy Huang; Stylianos Perissakis; Laura Pozzi 001; Joseph Yeh; John Wawrzynek (Microprocess. Microsystems, 2006)

Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Peng Jin; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (ICCD, 2007)

52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology. - Young Uk Yim; Peter F. Curran; Michael Chu; John F. McDonald 001; Russell P. Kraft (IET Circuits Devices Syst., 2007)

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Bryan S. Goda; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. - John F. McDonald 001; Okan Erdogan; Philip Jacob 001; Paul M. Belemjian; Alexey Gutin; Aamir Zia; Michael Chu; Jin Woo Kim; Ryan Clarke; Nate DeSimone; Sherry Liu; Russell P. Kraft (3DIC, 2009)

Scientific and Engineering Computing Using ATI Stream Technology. - Amr M. Bayoumi; Michael Chu; Yasser Y. Hanafy; Patricia Harrell; Gamal Refai-Ahmed (Comput. Sci. Eng., 2009)

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001; Kerry Bernstein (Proc. IEEE, 2009)

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology. - Michael Chu; Philip Jacob 001; Jin Woo Kim; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE J. Solid State Circuits, 2010)

Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology". - Michael Chu; Philip Jacob 001; Jin Woo Kim; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE J. Solid State Circuits, 2010)

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. - Aamir Zia; Philip Jacob 001; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications. - Jin Woo Kim; Michael Chu; Philip Jacob 001; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2011)

Carry Chains for Ultra High-Speed SiGe HBT Adders. - Alexey Gutin; Philip Jacob 001; Michael Chu; Paul M. Belemjian; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design of BiCMOS SRAMs for high-speed SiGe applications. - Xuelian Liu; Mitchell R. LeRoy; Ryan Clarke; Michael Chu; H. O. Aquino; Srikumar Raman; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2014)

Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology. - Xuelian Liu; Srikumar Raman; Ryan Clarke; Mitchell R. LeRoy; Okan Erdogan; Michael Chu; Alexey Gutin; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology. - Mitchell R. LeRoy; Srikumar Raman; Michael Chu; Jin Woo Kim; Jong-Ru Guo; Kuan Zhou; Chao You; Ryan Clarke; Bryan S. Goda; John F. McDonald 001 (Proc. IEEE, 2015)

Respiration rate and volume measurements using wearable strain sensors. - Michael Chu; Thao Nguyen; Vaibhav Pandey; Yongxiao Zhou; Hoang N. Pham; Ronen Bar-Yoseph; Shlomit Radom-Aizik; Ramesh C. Jain; Dan M. Cooper; Michelle Khine (npj Digit. Medicine, 2019)

Automated Detection of Underconstrained Circuits for Zero-Knowledge Proofs. - Shankara Pailoor; Yanju Chen; Franklyn Wang; Clara Rodríguez-Núñez; Jacob Van Gaffen; Jason Morton; Michael Chu; Brian Gu; Yu Feng 001; Isil Dillig (IACR Cryptol. ePrint Arch., 2023)

Automated Detection of Under-Constrained Circuits in Zero-Knowledge Proofs. - Shankara Pailoor; Yanju Chen; Franklyn Wang; Clara Rodríguez-Núñez; Jacob Van Geffen; Jason Morton; Michael Chu; Brian Gu; Yu Feng 001; Isil Dillig (Proc. ACM Program. Lang., 2023)

UnCLe: Unsupervised Continual Learning of Depth Completion. - Suchisrit Gangopadhyay; Xien Chen; Michael Chu; Patrick Rim; Hyoungseob Park; Alex Wong 001 (CoRR, 2024)