Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (ISLPED, 2000)

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (HPCA, 2001)

Reducing set-associative cache energy via way-prediction and selective direct-mapping. - Michael D. Powell; Amit Agarwal 001; T. N. Vijaykumar; Babak Falsafi; Kaushik Roy 001 (MICRO, 2001)

Reducing leakage in a high-performance deep-submicron instruction cache. - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; T. N. Vijaykumar (HPCA, 2002)

Reducing register ports for higher speed and lower energy. - Il Park 001; Michael D. Powell; T. N. Vijaykumar (MICRO, 2002)

Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. - Michael D. Powell; T. N. Vijaykumar (ISCA, 2003)

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. - Michael D. Powell; T. N. Vijaykumar (ISLPED, 2003)

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (MICRO, 2003)

Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. - Mohamed A. Gomaa; Michael D. Powell; T. N. Vijaykumar (ASPLOS, 2004)

Exploiting Resonant Behavior to Reduce Inductive Noise. - Michael D. Powell; T. N. Vijaykumar (ISCA, 2004)

Optimizing Replication, Communication, and Capacity Allocation in CMPs. - Zeshan Chishti; Michael D. Powell; T. N. Vijaykumar (ISCA, 2005)

Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. - Michael D. Powell; Ethan Schuchman; T. N. Vijaykumar (MICRO, 2005)

Resource area dilation to reduce power density in throughput servers. - Michael D. Powell; T. N. Vijaykumar (ISLPED, 2007)

CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. - Michael D. Powell; Arijit Biswas; Joel S. Emer; Shubhendu S. Mukherjee; Basit Riaz Sheikh; Shrirang M. Yardi (HPCA, 2009)

Architectural core salvaging in a multi-core processor for hard-error tolerance. - Michael D. Powell; Arijit Biswas; Shantanu Gupta; Shubhendu S. Mukherjee (ISCA, 2009)

Achieving uniform performance and maximizing throughput in the presence of heterogeneity. - Krishna K. Rangan; Michael D. Powell; Gu-Yeon Wei; David M. Brooks (HPCA, 2011)

Intel Xeon 6 Product Family. - Michael D. Powell; Patrick Fleming; Venkidesh Iyer Krishna; Naveen Lakkakula; Subhiksha Ravisundar; Praveen Mosur; Arijit Biswas; Pradeep Dubey; Kapil Sood; Andrew Cunningham; Smita Kumar (IEEE Micro, 2025)