A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. - Shenggao Li; Fulvio Spagna; Ji Chen; Xiaoqing Wang; Luke Tong; Sujatha Gowder; Wenyan Jia; Roan Nicholson; Sitaraman Iyer; Rui Song; Lily Li; Meng-hung Chen; et al. (A-SSCC, 2018)

A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. - Mike Bichan; Clifford Ting; Bahram Zand; Jing Wang; Ruslana Shulyzki; James Guthrie; Katya Tyshchenko; Junhong Zhao; Alireza Parsafar; Eric Liu; Aynaz Vatankhahghadim; Shaham Sharifian; et al. (CICC, 2020)

A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology. - Dong-Myung Choi; Yikui Dong; Roan Nicholson; Frank Liu 008; Wenyan Jia; Vadim Levin; Mike He; Sameer Pradhan; Jieqiong Du; Michael De Vita; Amanda Tran; Reza Navid; et al. (VLSI Technology and Circuits, 2024)