Partial Reconfiguration on FPGAs in Practice - Tools and Applications. - Dirk Koch; Jim Tørresen; Christian Beckhoff; Daniel Ziener; Christopher Dennl; Volker Breuer; Jürgen Teich; Michael Feilen; Walter Stechele (ARCS Workshops, 2012)

Partitioning and context switching for a reconfigurable FPGA-based DAB receiver. - Michael Feilen; Andreas Iliopoulos; Matthias Ihmig; Walter Stechele (DASIP, 2012)

Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios. - Matthias Ihmig; Michael Feilen; Andreas Herkersdorf (DSD, 2012)

Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. - Michael Feilen; Matthias Ihmig; Christian Schwarzbauer; Walter Stechele (FPL, 2012)

Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. - Michael Feilen; Andreas Iliopoulos; Michael Vonbun; Walter Stechele (FPL, 2013)

Evaluation of hop count advantages of network-coded 2D-mesh NoCs. - Michael Vonbun; Stefan Wallentowitz; Michael Feilen; Walter Stechele; Andreas Herkersdorf (PATMOS, 2013)

Wireless Channel Simulator Testbed for Airborne Receivers. - Steve Blandino; Florian Kaltenberger; Michael Feilen (GLOBECOM Workshops, 2015)