Layout and bias options for maximizing Vt1 in cascoded NMOS output buffers. - James W. Miller; Michael G. Khazhinsky; James C. Weldon (Microelectron. Reliab., 2001)

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies. - Cynthia A. Torres; James W. Miller; Michael Stockinger; Matthew D. Akers; Michael G. Khazhinsky; James C. Weldon (Microelectron. Reliab., 2002)

Advanced rail clamp networks for ESD protection. - Michael Stockinger; James W. Miller; Michael G. Khazhinsky; Cynthia A. Torres; James C. Weldon; Bryan D. Preble; Martin J. Bayer; Matthew D. Akers; Vishnu G. Kamat (Microelectron. Reliab., 2005)

ESD protection strategies in advanced CMOS SOI ICs. - Michael G. Khazhinsky (Microelectron. Reliab., 2007)

Electronic design automation (EDA) solutions for ESD-robust design and verification. - Michael G. Khazhinsky; Shuqing Cao; Harald Gossner; Gianluca Boselli; Melanie Etherton (CICC, 2012)