Power Considerations in the Design of the Alpha 21264 Microprocessor. - Michael K. Gowan; Larry L. Biro; Daniel B. Jackson (DAC, 1998)

Circuit implementation of a 600 MHz superscalar RISC microprocessor. - Mark Matson; Dan Bailey; Shane L. Bell; Larry L. Biro; Steve Butler; John Clouser; Jim Farrell; Mike Gowan; Donald A. Priore; Kathryn Wilcox (ICCD, 1998)

Testability access of the high speed test features in the Alpha 21264 microprocessor. - Dilip K. Bhavsar; David R. Akeson; Michael K. Gowan; Daniel B. Jackson (ITC, 1998)

High-performance microprocessor design. - Paul E. Gronowski; William J. Bowhill; Ronald P. Preston; Michael K. Gowan; Randy L. Allmon (IEEE J. Solid State Circuits, 1998)

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. - Joel Grodstein; Rachid Rayess; Tad Truex; Linda Shattuck; Sue Lowell; Dan Bailey; David Bertucci; Gabriel P. Bischoff; Daniel E. Dever; Mike Gowan; Roy Lane; Brian Lilly; et al. (ACM Great Lakes Symposium on VLSI, 2002)

A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. - Blaine A. Stackhouse; Brian S. Cherkauer; Michael K. Gowan; Paul E. Gronowski; Chris Lyles (ISSCC, 2008)

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. - Blaine A. Stackhouse; Sal Bhimji; Chris Bostak; Dave Bradley; Brian S. Cherkauer; Jayen Desai; Erin Francom; Mike Gowan; Paul E. Gronowski; Dan Krueger; Charles Morganti; Steve Troyer (IEEE J. Solid State Circuits, 2009)