Staging static analyses for program generation. - Sam Kamin; Baris Aktemur; Michael Katelman (GPCE, 2006)

A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis. - Michael Katelman; José Meseguer 001 (WRLA, 2006)

Getting Formal Verification into Design Flow. - Arvind 001; Nirav Dave; Michael Katelman (FM, 2008)

Redesign of the LMST Wireless Sensor Protocol through Formal Modeling and Statistical Model Checking. - Michael Katelman; José Meseguer 001; Jennifer C. Hou (FMOODS, 2008)

Directed-Logical Testing for Functional Verification of Microprocessors. - Michael Katelman; José Meseguer 001; Santiago Escobar 001 (MEMOCODE, 2008)

A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits. - Sean Keller; Michael Katelman; Alain J. Martin (ASYNC, 2009)

vlogsl: A Strategy Language for Simulation-Based Verification of Hardware. - Michael Katelman; José Meseguer 001 (Haifa Verification Conference, 2010)

A formal executable semantics of Verilog. - Patrick O'Neil Meredith; Michael Katelman; José Meseguer 001; Grigore Rosu (MEMOCODE, 2010)

Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits. - Michael Katelman; Sean Keller; José Meseguer 001 (WRLA, 2010)

Using the PALS Architecture to Verify a Distributed Topology Control Protocol for Wireless Multi-Hop Networks in the Presence of Node Failures - Michael Katelman; José Meseguer 001 (RTRTS, 2010)

Verification of microarchitectural refinements in rule-based systems. - Nirav Dave; Michael Katelman; Myron King; Arvind 001; José Meseguer 001 (MEMOCODE, 2011)

A meta-language for functional verification - Michael Katelman (2011)

Rewriting semantics of production rule sets. - Michael Katelman; Sean Keller; José Meseguer 001 (J. Log. Algebraic Methods Program., 2012)