DIF: A framework for VLSI multi-level representation. - David P. LaPotin; Sani R. Nassif; Jayanth V. Rajan; Michael L. Bushnell; John A. Nestor (Integr., 1984)

VLSI CAD tool integration using the Ulysses environment. - Michael L. Bushnell; Stephen W. Director (DAC, 1986)

Guest editorial. - Michael L. Bushnell; Pierre Haren (Artif. Intell. Eng., 1986)

ULYSSES - a knowledge-based VLSI design environment. - Michael L. Bushnell; Stephen W. Director (Artif. Intell. Eng., 1987)

A Module Area Estimator for VLSI Layout. - Xinghao Chen 003; Michael L. Bushnell (DAC, 1988)

Automatic test generation using neural networks. - Srimat T. Chakradhar; Michael L. Bushnell; Vishwani D. Agrawal (ICCAD, 1988)

Automated design tool execution in the Ulysses design environment. - Michael L. Bushnell; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. - Daniel R. Brasen; Michael L. Bushnell (DAC, 1990)

Automatic Test Generation Using Quadratic 0-1 Programming. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1990)

EST: The New Frontier in Automatic Test-Pattern Generation. - John Giraldi; Michael L. Bushnell (DAC, 1990)

Polynomial time solvable fault detection problems. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (FTCS, 1990)

Neural Net and Boolean Satisfiability Models of Logic Circuits. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell; Thomas K. Truong (IEEE Des. Test Comput., 1990)

Toward massively parallel automatic test generation. - Srimat T. Chakradhar; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Search State Equivalence for Redundancy Identification and Test Generation. - John Giraldi; Michael L. Bushnell (ITC, 1991)

Delay Fault Models and Test Generation for Random Logic Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1992)

A solvable class of quadratic 0-1 programming. - Srimat T. Chakradhar; Michael L. Bushnell (Discret. Appl. Math., 1992)

Design for Testability for Path Delay faults in Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1993)

An Efficient Path Delay Fault Coverage Estimator. - Keerthi Heragu; Michael L. Bushnell; Vishwani D. Agrawal (DAC, 1994)

Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. - Sandip Parikh; Michael L. Bushnell; James Sienicki; Ganesh Ramakrishnan (EDAC-ETC-EUROASIC, 1994)

Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. - Xinghao Chen 003; Michael L. Bushnell (FTCS, 1994)

Graphical Methodology Language for CAD Frameworks. - James Sienicki; Michael L. Bushnell; Sandip Parikh (VLSI Design, 1994)

Neural models for transistor and mixed-level test generation. - Carolina L. C. Cooper; Michael L. Bushnell (VTS, 1994)

FACTS: fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VTS, 1994)

Energy minimization and design for testability. - Srimat T. Chakradhar; Vishwani D. Agrawal; Michael L. Bushnell (J. Electron. Test., 1994)

Functional test generation for path delay faults. - Mandyam-Komar Srinivas; Vishwani D. Agrawal; Michael L. Bushnell (Asian Test Symposium, 1995)

An adaptive distributed algorithm for sequential circuit test generation. - James Sienicki; Michael L. Bushnell; Prathima Agrawal; Vishwani D. Agrawal (EURO-DAC, 1995)

Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 1995)

Generation of search state equivalence for automatic test pattern generation. - Xinghao Chen 003; Michael L. Bushnell (VLSI Design, 1995)

Statistical methods for delay fault coverage analysis. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 1995)

A graph approach to DFT hardware placement for robust delay fault BIST. - Imtiaz P. Shaik; Michael L. Bushnell (VLSI Design, 1995)

An asynchronous algorithm for sequential circuit test generation on a network of workstations. - James Sienicki; Michael L. Bushnell; Prathima Agrawal; Vishwani D. Agrawal (VLSI Design, 1995)

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . - Imtiaz P. Shaik; Michael L. Bushnell (VTS, 1995)

Fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Redundancy Identification Using Transitive Closure. - Vishwani D. Agrawal; Michael L. Bushnell; Qing Lin (Asian Test Symposium, 1996)

An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 1996)

Parallel concurrent path-delay fault simulation using single-input change patterns. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1996)

Statistical path delay fault coverage estimation for synchronous sequential circuits. - Lakshminarayana Pappu; Michael L. Bushnell; Vishwani D. Agrawal; Mandyam-Komar Srinivas (VLSI Design, 1996)

Sequential circuit test generation using dynamic justification equivalence. - Xinghao Chen 003; Michael L. Bushnell (J. Electron. Test., 1996)

Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. - Mandyam-Komar Srinivas; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1997)

A Functional Decomposition Method for Redundancy Identification and Test Generation. - Michael L. Bushnell; John Giraldi (J. Electron. Test., 1997)

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (J. Electron. Test., 1997)

On variable clock methods for path delay testing of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Improving a nonenumerative method to estimate path delay fault coverage. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

False-Path Removal Using Delay Fault Simulation. - Marwan A. Gharaybeh; Vishwani D. Agrawal; Michael L. Bushnell (Asian Test Symposium, 1998)

A non-enumerative path delay fault simulator for sequential circuits. - Carlos G. Parodi; Vishwani D. Agrawal; Michael L. Bushnell; Shianling Wu (ITC, 1998)

Path Delay Testing: Variable-Clock Versus Rated-Clock. - Subhashis Majumder; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 1998)

On Delay-Untestable Paths and Stuck-Fault Redundancy. - Subhashis Majumder; Vishwani D. Agrawal; Michael L. Bushnell (VTS, 1998)

Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. - Ganapathy Parthasarathy; Michael L. Bushnell (VTS, 1998)

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. - Lakshminarayana Pappu; Michael L. Bushnell; Vishwani D. Agrawal; Mandyam-Komar Srinivas (J. Electron. Test., 1998)

The path-status graph with application to delay fault simulation. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. - Marwan A. Gharaybeh; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Increasing Test Coverage in a VLSI Design Course. - Michael L. Bushnell (ITC, 1999)

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. - Vishwani D. Agrawal; Michael L. Bushnell; Ganapathy Parthasarathy; Rajesh Ramadoss (VLSI Design, 1999)

A Complete Characterization of Path Delay Faults through Stuck-at Faults. - Subhashis Majumder; Bhargab B. Bhattacharya; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 1999)

Effect of Noise on Analog Circuit Testing. - Madhu K. Iyer; Michael L. Bushnell (J. Electron. Test., 1999)

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. - Rajesh Ramadoss; Michael L. Bushnell (J. Electron. Test., 1999)

False-Path Removal Using Delay Fault Simulation. - Marwan A. Gharaybeh; Vishwani D. Agrawal; Michael L. Bushnell; Carlos G. Parodi (J. Electron. Test., 2000)

Path delay fault simulation of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Improving path delay testability of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A Code Transition Delay Model for ADC Test. - Sanjay Mohan; Michael L. Bushnell (VLSI Design, 2001)

A New Transitive Closure Algorithm with Application to Redundancy Identification. - Vivek Gaur; Vishwani D. Agrawal; Michael L. Bushnell (DELTA, 2002)

Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. - Aditya D. Sathe; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 2002)

Electronic Testing for SOC Designers (Tutorial Abstract). - Vishwani D. Agrawal; Michael L. Bushnell (ASP-DAC/VLSI Design, 2002)

A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. - Vishal J. Mehta; Kunal K. Dave; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2003)

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2003)

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. - Lan Rao; Michael L. Bushnell; Vishwani D. Agrawal (VLSI Design, 2003)

Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. - Omar I. Khan; Michael L. Bushnell (ITC, 2004)

On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. - Junwu Zhang; Michael L. Bushnell; Vishwani D. Agrawal (ITC, 2004)

A Tuturial on the Emerging Nanotechnology Devices. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2004)

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2004)

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. - Subhashis Majumder; Bhargab B. Bhattacharya; Vishwani D. Agrawal; Michael L. Bushnell (J. Comput. Sci. Technol., 2004)

Design of Variable Input Delay Gates for Low Dynamic Power Circuits. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (PATMOS, 2005)

Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. - Kunal K. Dave; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 2005)

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. - Rajamani Sethuram; Seongmoon Wang; Srimat T. Chakradhar; Michael L. Bushnell (ATS, 2006)

A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. - Baozhen Yu; Michael L. Bushnell (ISLPED, 2006)

Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. - Shweta Chary; Michael L. Bushnell (VLSI Design, 2006)

Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. - Shweta Chary; Michael L. Bushnell (VLSI Design, 2006)

Sequential Spectral ATPG Using the Wavelet Transform and Compaction. - Suresh Kumar Devanathan; Michael L. Bushnell (VLSI Design, 2006)

Aliasing Analysis of Spectral Statistical Response Compaction Techniques. - Omar I. Khan; Michael L. Bushnell (VLSI Design, 2006)

An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. - Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2006)

Transistor Sizing of Logic Gates to Maximize Input Delay Variability. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (J. Low Power Electron., 2006)

Power Grid Analysis of Dynamic Power Cutoff Technology. - Baozhen Yu; Michael L. Bushnell (ISCAS, 2007)

SPARTAN: a spectral and information theoretic approach to partial-scan. - Omar I. Khan; Michael L. Bushnell; Suresh Kumar Devanathan; Vishwani D. Agrawal (ITC, 2007)

Analog Circuit Testing Using Auto Regressive Moving Average Models. - Jeffrey Ayres; Michael L. Bushnell (VLSI Design, 2007)

Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. - Suresh Kumar Devanathan; Michael L. Bushnell (VLSI Design, 2007)

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. - Daniel Mazor; Michael L. Bushnell; David J. Mulligan; Richard J. Blaikie (VLSI Design, 2007)

Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. - Rohit Pandey; Michael L. Bushnell (VLSI Design, 2007)

A Neural Net Branch Predictor to Reduce Power. - Rajamani Sethuram; Omar I. Khan; Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2007)

Zero Cost Test Point Insertion Technique for Structured ASICs. - Rajamani Sethuram; Seongmoon Wang; Srimat T. Chakradhar; Michael L. Bushnell (VLSI Design, 2007)

Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. - Lan Rao; Michael L. Bushnell; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. - Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2008)

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. - Rajamani Sethuram; Michael L. Bushnell; Vishwani D. Agrawal (VTS, 2008)

Variable Input Delay CMOS Logic for Low Power Design. - Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2009)