Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. - Arkadiy Morgenshtein; Michael Moreinis; Israel A. Wagner; Avinoam Kolodny (VLSI-SOC, 2003)

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. - Michael Moreinis; Arkadiy Morgenshtein; Israel A. Wagner; Avinoam Kolodny (ICECS, 2004)

Asynchronous gate-diffusion-input (GDI) circuits. - Arkadiy Morgenshtein; Michael Moreinis; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. - Michael Moreinis; Arkadiy Morgenshtein; Israel A. Wagner; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2006)