Design of optimal systolic arrays: a systematic approach. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (SPDP, 1990)

Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (ICPP (1), 1991)

On the Design of Optimal Fault-Tolerant Systolic Array Architecures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (IPPS, 1991)

Design Methodology for Fault-Tolerant Systolic Array Architectures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (ICPP (2), 1992)

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. - Michael Ogbonna Esonu; Dhamin Al-Khalili; Côme Rozon (VLSI Design, 1994)

Area efficient computing structures for concurrent error detection in systolic arrays. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (J. VLSI Signal Process., 1995)

Design techniques for fault-tolerant systolic arrays. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri; Dhamin Al-Khalili (J. VLSI Signal Process., 1995)