A 1.2- mu m CMOS current-controlled oscillator. - Michael P. Flynn; Sverre U. Lidholm (IEEE J. Solid State Circuits, 1992)

CMOS folding A/D converters with current-mode interpolation. - Michael P. Flynn; David J. Allstot (IEEE J. Solid State Circuits, 1996)

A 400-Msample/s, 6-b CMOS folding and interpolating ADC. - Michael P. Flynn; Ben Sheahan (IEEE J. Solid State Circuits, 1998)

A BiCMOS preamplifier/write-driver IC for tape drive. - Michael P. Flynn; Michael Twohig; Raymond Byrne; Hooman Reyhani; John Ryan (CICC, 1999)

A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS. - David J. Foley; Michael P. Flynn (ISCAS, 2000)

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. - David J. Foley; Michael P. Flynn (IEEE J. Solid State Circuits, 2001)

A "digital" 6-bit ADC in 0.25-μm CMOS. - Conor Donovan; Michael P. Flynn (IEEE J. Solid State Circuits, 2002)

A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. - David J. Foley; Michael P. Flynn (IEEE J. Solid State Circuits, 2002)

Digital calibration incorporating redundancy of flash ADCs. - Michael P. Flynn; Conor Donovan; L. Sattler (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

An RF powered, wireless temperature sensor in quarter micron CMOS. - Fatih Kocer; Paul M. Walsh; Michael P. Flynn (ISCAS (4), 2004)

A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (CICC, 2005)

A new transponder architecture for long-range telemetry applications. - Fatih Kocer; Michael P. Flynn (ECCTD, 2005)

Design techniques for high performance CMOS flash analog-to-digital converters. - Sunghyun Park 006; Michael P. Flynn (ECCTD, 2005)

Global signaling over lossy transmission lines. - Michael P. Flynn; Joshua Jaeyoung Kang (ICCAD, 2005)

Capacitively averaged multi-phase LC oscillators. - JunYoung Park; Michael P. Flynn (ISCAS (3), 2005)

A Low Jitter Multi-Phase PLL with Capacitive Coupling. - JunYoung Park; Michael P. Flynn (CICC, 2006)

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Ashoke Ravi; Ralph E. Bishop; Michael P. Flynn (CICC, 2006)

A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (ISSCC, 2006)

A 4GS/s 4b Flash ADC in 0.18µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (ISSCC, 2006)

A new transponder architecture with on-chip ADC for long-range telemetry applications. - Fatih Kocer; Michael P. Flynn (IEEE J. Solid State Circuits, 2006)

A regenerative comparator structure with integrated inductors. - Sunghyun Park 006; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. - Ivan Bogue; Michael P. Flynn (CICC, 2007)

A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. - Mark A. Ferriss; Michael P. Flynn (ISSCC, 2007)

A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (IEEE J. Solid State Circuits, 2007)

A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (IEEE J. Solid State Circuits, 2007)

A reconfigurable FIR filter embedded in a 9b successive approximation ADC. - Joshua Jaeyoung Kang; David T. Lin; Li Li; Michael P. Flynn (CICC, 2008)

A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. - JunYoung Park; Joshua Jaeyoung Kang; Sunghyun Park 006; Michael P. Flynn (CICC, 2008)

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. - Mark A. Ferriss; Michael P. Flynn (IEEE J. Solid State Circuits, 2008)

A fractional-N PLL modulator with flexible direct digital phase modulation. - Mark A. Ferriss; David T. Lin; Michael P. Flynn (CICC, 2009)

A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS. - Shahrzad Naraghi; Matthew Courcy; Michael P. Flynn (ISSCC, 2009)

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. - Jongwoo Lee; Joshua Jaeyoung Kang; Sunghyun Park 006; Jae-sun Seo; Jens Anders; Jorge Guilherme; Michael P. Flynn (IEEE J. Solid State Circuits, 2009)

A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. - JunYoung Park; Joshua Jaeyoung Kang; Sunghyun Park 006; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC. - David T. Lin; Li Li; Shahin Farahani; Michael P. Flynn (CICC, 2010)

An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS. - Andres Tamez; Jeffrey A. Fredenburg; Michael P. Flynn (ESSCIRC, 2010)

A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. - Jongwoo Lee; Hyo-Gyuem Rhew; Daryl R. Kipke; Michael P. Flynn (IEEE J. Solid State Circuits, 2010)

A 9-bit, 14 μW and 0.06 mm 2 Pulse Position Modulation ADC in 90 nm Digital CMOS. - Shahrzad Naraghi; Matthew Courcy; Michael P. Flynn (IEEE J. Solid State Circuits, 2010)

Rand PPM: A lowpower compressive sampling analog to digital converter. - Praveen K. Yenduri; Anna C. Gilbert; Michael P. Flynn; Shahrzad Naraghi (ICASSP, 2011)

A SAR-Assisted Two-Stage Pipeline ADC. - Chun C. Lee; Michael P. Flynn (IEEE J. Solid State Circuits, 2011)

A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC. - Chun C. Lee; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. - Jorge Pernillo; Michael P. Flynn (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. - Hyo-Gyuem Rhew; Michael P. Flynn; JunYoung Park (ESSCIRC, 2012)

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. - Hyungil Chae; Jaehun Jeong; Gabriele Manganaro; Michael P. Flynn (ISSCC, 2012)

A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. - Jeffrey Fredenburg; Michael P. Flynn (ISSCC, 2012)

A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. - Hyo-Gyuem Rhew; Jaehun Jeong; Jeffrey A. Fredenburg; Sunjay Dodani; Parag G. Patil; Michael P. Flynn (VLSIC, 2012)

A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter. - Praveen K. Yenduri; Aaron Z. Rocca; Aswin S. Rao; Shahrzad Naraghi; Michael P. Flynn; Anna C. Gilbert (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. - Jeffrey Fredenburg; Michael P. Flynn (IEEE J. Solid State Circuits, 2012)

Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch. - Jeffrey Fredenburg; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC. - David T. Lin; Li Li; Shahin Farahani; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 9b 2GS/s 45mW 2X-interleaved ADC. - Jorge Pernillo; Michael P. Flynn (ESSCIRC, 2013)

EP2: You're hired! The top 25 interview questions for circuit designers. - Michael P. Flynn; John Khoury (ISSCC, 2013)

Message From the Incoming Editor-in-Chief. - Michael P. Flynn (IEEE J. Solid State Circuits, 2013)

11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. - Yong Lim; Michael P. Flynn (ISSCC, 2014)

An N-path filter enhanced low phase noise ring VCO. - Chunyang Zhai; Jeffrey Fredenburg; John Bell; Michael P. Flynn (VLSIC, 2014)

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. - Hyungil Chae; Jaehun Jeong; Gabriele Manganaro; Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

New Associate Editors. - Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

New Associate Editor [Ken Suyama]. - Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. - Hyo-Gyuem Rhew; Jaehun Jeong; Jeffrey A. Fredenburg; Sunjay Dodani; Parag G. Patil; Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

ADC trends and impact on SAR ADC architecture and analysis. - Jeffrey Fredenburg; Michael P. Flynn (CICC, 2015)

A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution. - Mehmet Batuhan Dayanik; Nicholas Collins; Michael P. Flynn (ESSCIRC, 2015)

26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC. - Yong Lim; Michael P. Flynn (ISSCC, 2015)

Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression. - Adam E. Mendrela; Jihyun Cho; Jeffrey A. Fredenburg; Cynthia A. Chestek; Michael P. Flynn; Euisik Yoon (VLSIC, 2015)

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. - Yong Lim; Michael P. Flynn (IEEE J. Solid State Circuits, 2015)

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC. - Yong Lim; Michael P. Flynn (IEEE J. Solid State Circuits, 2015)

27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. - Kyojin David Choo; John Bell; Michael P. Flynn (ISSCC, 2016)

A 16-channel noise-shaping machine learning analog-digital interface. - Fred N. Buhler; Adam E. Mendrela; Yong Lim; Jeffrey A. Fredenburg; Michael P. Flynn (VLSI Circuits, 2016)

A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. - Hyungil Chae; Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

New Associate Editor. - Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC. - Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

Introducing Short Regular Papers. - Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

Message From the Outgoing Editor-in-Chief. - Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

New Associate Editors. - Michael P. Flynn; Pietro Andreani; SeongHwan Cho (IEEE J. Solid State Circuits, 2016)

A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators. - Jaehun Jeong; Nicholas Collins; Michael P. Flynn (IEEE J. Solid State Circuits, 2016)

A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. - Adam E. Mendrela; Jihyun Cho; Jeffrey A. Fredenburg; Vivek Nagaraj; Theoden I. Netoff; Michael P. Flynn; Euisik Yoon (IEEE J. Solid State Circuits, 2016)

A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. - John Bell; Phil Knag; Shuanghong Sun; Yong Lim; Thomas Chen 003; Jeffrey Fredenburg; Chia-Hsiang Chen; Chunyang Zhai; Aaron Z. Rocca; Nicholas Collins; Andres Tamez; Jorge Pernillo; et al. (IEEE J. Solid State Circuits, 2017)

A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. - Yashar Rajavi; Mohammad Mahdi Ghahramani; Alireza Khalili; Amirpouya Kavousian; Beomsup Kim; Michael P. Flynn (IEEE J. Solid State Circuits, 2017)

A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. - Daniel Weyer; Mehmet Batuhan Dayanik; Sunmin Jang; Michael P. Flynn (ISSCC, 2018)

A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. - Adam E. Mendrela; Sung-Yun Park; Mihály Vöröslakos; Michael P. Flynn; Euisik Yoon (VLSI Circuits, 2018)

Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System. - Mehmet Batuhan Dayanik; Michael P. Flynn (IEEE J. Solid State Circuits, 2018)

A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS. - Sunmin Jang; Jaehun Jeong; Rundao Lu; Michael P. Flynn (IEEE J. Solid State Circuits, 2018)

A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. - Nicholas Collins; Andres Tamez; Lu Jie 001; Jorge Pernillo; Michael P. Flynn (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. - Shiming Song 002; Kyojin David Choo; Thomas Chen 003; Sunmin Jang; Michael P. Flynn; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS. - John Bell; Michael P. Flynn (ESSCIRC, 2019)

A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC. - Lu Jie 001; Boyi Zheng; Michael P. Flynn (ISSCC, 2019)

Design Considerations for Integrated Radar Chirp Synthesizers. - Daniel Weyer; Mehmet Batuhan Dayanik; Lu Jie 001; Ahmed Albalawi; Abdulhamed Alothaimen; Mohammed Aseeri; Michael P. Flynn (IEEE Access, 2019)

A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer. - Sunmin Jang; Rundao Lu; Jaehun Jeong; Michael P. Flynn (IEEE J. Solid State Circuits, 2019)

A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. - Lu Jie 001; Boyi Zheng; Michael P. Flynn (IEEE J. Solid State Circuits, 2019)

A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS. - Peter Lawrence Brown; Matthew R. O'Shaughnessy; Christopher J. Rozell; Justin Romberg; Michael P. Flynn (CICC, 2020)

Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited). - Michael P. Flynn; Jaehun Jeong; Sunmin Jang; Hyungil Chae; Daniel Weyer; Rundao Lu; John Bell (CICC, 2020)

9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. - Lu Jie 001; Boyi Zheng; Hsiang-Wen Chen; Runyu Wang; Michael P. Flynn (ISSCC, 2020)

An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. - Seungjong Lee; Taewook Kang; John Bell; Mohammad R. Haghighat; Alberto J. Martinez; Michael P. Flynn (VLSI Circuits, 2020)

A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. - Lu Jie 001; Boyi Zheng; Hsiang-Wen Chen; Michael P. Flynn (IEEE J. Solid State Circuits, 2020)

A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. - Taewook Kang; Seungjong Lee; Mohammad Haghigat; Darren Abramson 002; Michael P. Flynn (CICC, 2021)

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. - Boyi Zheng; Lu Jie 001; Michael P. Flynn (ESSCIRC, 2021)

10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. - Lu Jie 001; Hsiang-Wen Chen; Boyi Zheng; Michael P. Flynn (ISSCC, 2021)

A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS. - Rundao Lu; Michael P. Flynn (VLSI Circuits, 2021)

A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. - Peter Lawrence Brown; Matthew R. O'Shaughnessy; Christopher Rozell; Justin Romberg; Michael P. Flynn (IEEE J. Solid State Circuits, 2021)

A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. - Lu Jie 001; Hsiang-Wen Chen; Boyi Zheng; Michael P. Flynn (IEEE J. Solid State Circuits, 2021)

A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver. - Rundao Lu; Christine Weston; Daniel Weyer; Fred N. Buhler; Daniel Lambalot; Michael P. Flynn (IEEE J. Solid State Circuits, 2021)

Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver". - Rundao Lu; Christine Weston; Daniel Weyer; Fred N. Buhler; Daniel Lambalot; Michael P. Flynn (IEEE J. Solid State Circuits, 2021)

6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration. - Evelyn Ware; Justin M. Correll; Seungjong Lee; Michael P. Flynn (ESSCIRC, 2022)

A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. - Taewook Kang; Seungjong Lee; Seungheun Song; Mohammad R. Haghighat; Michael P. Flynn (ISSCC, 2022)

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (VLSI Technology and Circuits, 2022)

An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. - Seungjong Lee; Taewook Kang; John Bell; Mohammad R. Haghighat; Alberto J. Martinez; Michael P. Flynn (IEEE J. Solid State Circuits, 2022)

TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. - Xinxin Wang 002; Reid Pinkham; Mohammed Affan Zidan; Fan-Hsuan Meng; Michael P. Flynn; Zhengya Zhang; Wei D. Lu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM). - Hsiang-Wen Chen; Seungjong Lee; Michael P. Flynn (VLSI Technology and Circuits, 2023)

A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C. - Seungheun Song; Taewook Kang; Seungjong Lee; Michael P. Flynn (VLSI Technology and Circuits, 2023)

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (IEEE J. Solid State Circuits, 2023)

A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC. - Rundao Lu; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental sΔΔ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking. - Sungjin Oh; Hyunsoo Song; Jose Roberto Lopez Ruiz; Wangbo Chen; Sung-Yun Park; Michael P. Flynn; Euisik Yoon (VLSI Technology and Circuits, 2024)

An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. - Hsiang-Wen Chen; Seungjong Lee; Michael P. Flynn (IEEE J. Solid State Circuits, 2024)

A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer. - Taewook Kang; Seungjong Lee; Seungheun Song; Mohammad Reza Haghighat; Michael P. Flynn (IEEE J. Solid State Circuits, 2024)

25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time. - Evangelos Dikopoulos; Ying-Tuan Hsu; Luke Wormald; Wei Tang 010; Zhengya Zhang; Michael P. Flynn (ISSCC, 2025)

A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector. - Matthew R. Belz; Zhengqi Xu; Hsiang-Wen Chen; Seungheun Song; Michael P. Flynn (IEEE J. Solid State Circuits, 2025)

RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes. - Evangelos Dikopoulos; Luke Wormald; Ying-Tuan Hsu; Wei Tang 010; Po-Shao Chen; Zhengya Zhang; Michael P. Flynn (IEEE J. Solid State Circuits, 2025)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)