Prototyping Efficient Interprocessor Communication Mechanisms. - Vassilis Papaefstathiou; Dionisios N. Pnevmatikatos; Manolis Marazakis; Giorgos Kalokairinos; Aggelos Ioannou; Michael Papamichael; Stamatis G. Kavadias; Giorgos Mihelogiannakis; Manolis Katevenis (ICSAMOS, 2007)

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. - Eric S. Chung; Michael Papamichael; Eriko Nurvitadhi; James C. Hoe; Ken Mai; Babak Falsafi (ACM Trans. Reconfigurable Technol. Syst., 2009)

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. - Yoongu Kim; Michael Papamichael; Onur Mutlu; Mor Harchol-Balter (MICRO, 2010)

Fast scalable FPGA-based Network-on-Chip simulation models. - Michael Papamichael (MEMOCODE, 2011)

FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. - Michael Papamichael; James C. Hoe; Onur Mutlu (NOCS, 2011)

Thread Cluster Memory Scheduling. - Yoongu Kim; Michael Papamichael; Onur Mutlu; Mor Harchol-Balter (IEEE Micro, 2011)

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. - Eric S. Chung; Michael Papamichael; Gabriel Weisz; James C. Hoe; Ken Mai (FPGA, 2012)

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. - Michael Papamichael; James C. Hoe (FPGA, 2012)

ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects. - Eric S. Chung; Michael Papamichael (FCCM, 2013)

Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only). - Eric S. Chung; Michael Papamichael (FPGA, 2013)

Cross-platform FPGA accelerator development using CoRAM and CONNECT. - Eric S. Chung; Michael Papamichael; Gabriel Weisz; James C. Hoe (FPGA, 2013)

Nautilus: fast automated IP design space search using guided genetic algorithms. - Michael K. Papamichael; Peter A. Milder; James C. Hoe (DAC, 2015)

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. - Michael Papamichael; Cagla Cakir; Chen Sun 003; Chia-Hsin Owen Chen; James C. Hoe; Ken Mai; Li-Shiuan Peh; Vladimir Stojanovic (ISPASS, 2015)

The CONNECT Network-on-Chip Generator. - Michael K. Papamichael; James C. Hoe (Computer, 2015)

Agile Co-Design for a Reconfigurable Datacenter. - Shlomi Alkalay; Hari Angepat; Adrian M. Caulfield; Eric S. Chung; Oren Firestein; Michael Haselman; Stephen Heil; Kyle Holohan; Matt Humphrey; Tamás Juhász; Puneet Kaur; Sitaram Lanka; et al. (FPGA, 2016)

A cloud-scale acceleration architecture. - Adrian M. Caulfield; Eric S. Chung; Andrew Putnam; Hari Angepat; Jeremy Fowers; Michael Haselman; Stephen Heil; Matt Humphrey; Puneet Kaur; Joo-Young Kim 001; Daniel Lo; Todd Massengill; et al. (MICRO, 2016)

HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics. - Jiayi Sheng; Chen Yang 010; Ahmed Sanaullah; Michael Papamichael; Adrian M. Caulfield; Martin C. Herbordt (FPL, 2017)

Configurable Clouds. - Adrian M. Caulfield; Eric S. Chung; Andrew Putnam; Hari Angepat; Daniel Firestone; Jeremy Fowers; Michael Haselman; Stephen Heil; Matt Humphrey; Puneet Kaur; Joo-Young Kim 001; Daniel Lo; et al. (IEEE Micro, 2017)

A Configurable Cloud-Scale DNN Processor for Real-Time AI. - Jeremy Fowers; Kalin Ovtcharov; Michael Papamichael; Todd Massengill; Ming Liu; Daniel Lo; Shlomi Alkalay; Michael Haselman; Logan Adams; Mahdi Ghandi; Stephen Heil; Prerak Patel; et al. (ISCA, 2018)

Serving DNNs in Real Time at Datacenter Scale with Project Brainwave. - Eric S. Chung; Jeremy Fowers; Kalin Ovtcharov; Michael Papamichael; Adrian M. Caulfield; Todd Massengill; Ming Liu; Daniel Lo; Shlomi Alkalay; Michael Haselman; Maleen Abeydeera; Logan Adams; et al. (IEEE Micro, 2018)

Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor. - Jeremy Fowers; Kalin Ovtcharov; Michael K. Papamichael; Todd Massengill; Ming Liu; Daniel Lo; Shlomi Alkalay; Michael Haselman; Logan Adams; Mahdi Ghandi; Stephen Heil; Prerak Patel; et al. (IEEE Micro, 2019)

SMaRTT-REPS: Sender-based Marked Rapidly-adapting Trimmed & Timed Transport with Recycled Entropies. - Tommaso Bonato; Abdul Kabbani; Daniele De Sensi; Rong Pan; Yanfang Le; Costin Raiciu; Mark Handley; Timo Schneider; Nils Blach; Ahmad Ghalayini; Daniel S. F. Alves; Michael Papamichael; et al. (CoRR, 2024)

REPS: Recycling Entropies for Packet Spraying to Adaptively Explore Paths and Mitigate Failures. - Tommaso Bonato; Abdul Kabbani; Ahmad Ghalayini; Mohammad Dohadwala; Michael Papamichael; Daniele De Sensi; Torsten Hoefler (CoRR, 2024)