Systematischer Entwurf von Makroprozessoren. - Michael Payer (GI Jahrestagung, 1980)

Verification and validation of hierarchical CMOS gate array layouts. - Michael Payer (Microprocess. Microprogramming, 1987)

Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen. - Michael Payer (GI Jahrestagung (2), 1988)

A system for estimation of numerical stability for matrix operations in systolic arrays. - Reinhard H. Rauscher; Peter Kückendahl; Michael Payer (Microprocess. Microprogramming, 1988)

Finite State Machine Theory as a Tool for Construction of Systolic Arrays. - Michael Payer (EUROCAST, 1989)

Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-Technik. - Michael Payer (1989)

Data-Path Synthesis Using Path Analysis. - Reinaldo A. Bergamaschi; Raul Camposano; Michael Payer (DAC, 1991)

Area and performance optimizations in path-based scheduling. - Reinaldo A. Bergamaschi; Raul Camposano; Michael Payer (EURO-DAC, 1991)

Scheduling under resource constraints and module assignment. - Reinaldo A. Bergamaschi; Raul Camposano; Michael Payer (Integr., 1991)

Partitioning and ordering of CMOS circuits for switch level analysis. - Michael Payer (Integr., 1991)

Data Part Optimizations in the CALLAS Synthesis Environment. - Jörg Biesenack; Norbert Wehn; A. Stoll; Michael Payer (Synthesis for Control Dominated Circuits, 1992)

Allocation algorithms based on path analysis. - Reinaldo A. Bergamaschi; Raul Camposano; Michael Payer (Integr., 1992)

The Siemens high-level synthesis system CALLAS. - Jörg Biesenack; Michael Koster; Anton Langmaier; Stephane Ledeux; Sabine März; Michael Payer; Michael Pilsl; Steffen Rumler; Holger Soukup; Norbert Wehn; Peter Duzy (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Model Checking in Industrial Hardware Design. - Jörg Bormann; Jörg Lohse; Michael Payer; Gerd Venzl (DAC, 1995)

Industrial Experience with Formal Verification. - Michael Payer (MBMV, 2000)

Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation). - Michael Payer (Informationstechnik Tech. Inform., 2001)

A Platform for Construction and Integration of Digital IP Blocks. - Michael Payer (MBMV, 2003)