Synthesis of synchronous assertions with guarded atomic actions. - Michael Pellauer; Mieszko Lis; Don Baltus; Rishiyur S. Nikhil (MEMOCODE, 2005)

802.11a transmitter: a case study in microarchitectural exploration. - Nirav Dave; Michael Pellauer; S. Gerding; Arvind 001 (MEMOCODE, 2006)

Scheduling as Rule Composition. - Nirav Dave; Arvind 001; Michael Pellauer (MEMOCODE, 2007)

Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. - Nirav Dave; Kermin Fleming; Myron King; Michael Pellauer; Muralidaran Vijayaraghavan (MEMOCODE, 2007)

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (FPGA, 2008)

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ISPASS, 2008)

Soft connections: addressing the hardware-design modularity problem. - Michael Pellauer; Michael Adler; Derek Chiou; Joel S. Emer (DAC, 2009)

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ACM Trans. Reconfigurable Technol. Syst., 2009)

A design flow based on modular refinement. - Nirav Dave; Man Cheuk Ng; Michael Pellauer; Arvind 001 (MEMOCODE, 2010)

Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). - Michael Pellauer; Abhinav Agarwal; Asif Khan 005; Man Cheuk Ng; Muralidaran Vijayaraghavan; Forrest Brewer; Joel S. Emer (MEMOCODE, 2010)

Leap scratchpads: automatic memory and cache management for reconfigurable logic. - Michael Adler; Kermin Fleming; Angshuman Parashar; Michael Pellauer; Joel S. Emer (FPGA, 2011)

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. - Michel A. Kinsy; Michael Pellauer; Srinivas Devadas (FPL, 2011)

HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. - Michael Pellauer; Michael Adler; Michel A. Kinsy; Angshuman Parashar; Joel S. Emer (HPCA, 2011)

Cycle-accurate multicore performance models on FPGAs. - Michael Pellauer (2011)

Leveraging latency-insensitivity to ease multiple FPGA design. - Kermin Elliott Fleming; Michael Adler; Michael Pellauer; Angshuman Parashar; Arvind 001; Joel S. Emer (FPGA, 2012)

Heracles: a tool for fast RTL-based design space exploration of multicore processors. - Michel A. Kinsy; Michael Pellauer; Srinivas Devadas (FPGA, 2013)

A Hierarchical Architectural Framework for Reconfigurable Logic Computing. - Peng Li 031; Angshuman Parashar; Michael Pellauer; Tao Wang 004; Joel S. Emer (IPDPS Workshops, 2013)

Triggered instructions: a control paradigm for spatially-programmed architectures. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (ISCA, 2013)

Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. - Daniel Lustig; Michael Pellauer; Margaret Martonosi (MICRO, 2014)

Efficient Spatial Processing Element Control via Triggered Instructions. - Angshuman Parashar; Michael Pellauer; Michael Adler; Bushra Ahsan; Neal Clayton Crago; Daniel Lustig; Vladimir Pavlov; Antonia Zhai; Mohit Gambhir; Aamer Jaleel; Randy L. Allmon; Rachid Rayess; et al. (IEEE Micro, 2014)

ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. - Daniel Lustig; Caroline Trippel; Michael Pellauer; Margaret Martonosi (ISCA, 2015)

CCICheck: using µhb graphs to verify the coherence-consistency interface. - Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (MICRO, 2015)

Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. - Daniel Lustig; Michael Pellauer; Margaret Martonosi (IEEE Micro, 2015)

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. - Michael Pellauer; Angshuman Parashar; Michael Adler; Bushra Ahsan; Randy L. Allmon; Neal Clayton Crago; Kermin Fleming; Mohit Gambhir; Aamer Jaleel; Tushar Krishna; Daniel Lustig; Stephen Maresh; et al. (ACM Trans. Comput. Syst., 2015)

Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. - Yatin A. Manerkar; Caroline Trippel; Daniel Lustig; Michael Pellauer; Margaret Martonosi (CoRR, 2016)

Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (CoRR, 2016)

TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (ASPLOS, 2017)

RTLcheck: verifying the memory consistency of RTL designs. - Yatin A. Manerkar; Daniel Lustig; Margaret Martonosi; Michael Pellauer (MICRO, 2017)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. - Kartik Hegde; Jiyong Yu; Rohit Agrawal 001; Mengjia Yan 001; Michael Pellauer; Christopher W. Fletcher (ISCA, 2018)

MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators. - Hyoukjun Kwon; Michael Pellauer; Tushar Krishna (CoRR, 2018)

Full-Stack Memory Model Verification with TriCheck. - Caroline Trippel; Yatin A. Manerkar; Daniel Lustig; Michael Pellauer; Margaret Martonosi (IEEE Micro, 2018)

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. - Michael Pellauer; Yakun Sophia Shao; Jason Clemons; Neal Clayton Crago; Kartik Hegde; Rangharajan Venkatesan; Stephen W. Keckler; Christopher W. Fletcher; Joel S. Emer (ASPLOS, 2019)

ExTensor: An Accelerator for Sparse Tensor Algebra. - Kartik Hegde; Hadi Asghari Moghaddam; Michael Pellauer; Neal Clayton Crago; Aamer Jaleel; Edgar Solomonik; Joel S. Emer; Christopher W. Fletcher (MICRO, 2019)

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. - Hyoukjun Kwon; Prasanth Chatarasi; Michael Pellauer; Angshuman Parashar; Vivek Sarkar; Tushar Krishna (MICRO, 2019)

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings. - Hyoukjun Kwon; Prasanth Chatarasi; Vivek Sarkar; Tushar Krishna; Michael Pellauer; Angshuman Parashar (IEEE Micro, 2020)

Data Orchestration in Deep Learning Accelerators - Tushar Krishna; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Ananda Samajdar (Morgan & Claypool Publishers, 2020)

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads. - Hyoukjun Kwon; Liangzhen Lai; Michael Pellauer; Tushar Krishna; Yu-Hsin Chen; Vikas Chandra (HPCA, 2021)

Flexion: A Quantitative Metric for Flexibility in DNN Accelerators. - Hyoukjun Kwon; Michael Pellauer; Angshuman Parashar; Tushar Krishna (IEEE Comput. Archit. Lett., 2021)

Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration. - Ananda Samajdar; Michael Pellauer; Tushar Krishna (CoRR, 2021)

Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. - Ananda Samajdar; Eric Qin 001; Michael Pellauer; Tushar Krishna (DAC, 2022)

DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. - Sheng-Chun Kao; Michael Pellauer; Angshuman Parashar; Tushar Krishna (DATE, 2022)

Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. - Eric Qin 001; Raveesh Garg; Abhimanyu Bambhaniya; Michael Pellauer; Angshuman Parashar; Sivasankaran Rajamanickam; Cong Hao; Tushar Krishna (CoRR, 2022)

A Formalism of DNN Accelerator Flexibility. - Sheng-Chun Kao; Hyoukjun Kwon; Michael Pellauer; Angshuman Parashar; Tushar Krishna (Proc. ACM Meas. Anal. Comput. Syst., 2022)

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. - Prasanth Chatarasi; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Tushar Krishna; Vivek Sarkar (ACM Trans. Archit. Code Optim., 2022)

Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. - Francisco Muñoz-Martínez; Raveesh Garg; Michael Pellauer; José L. Abellán; Manuel E. Acacio; Tushar Krishna (ASPLOS (3), 2023)

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. - Toluwanimi O. Odemuyiwa; Hadi Asghari Moghaddam; Michael Pellauer; Kartik Hegde; Po-An Tsai; Neal Clayton Crago; Aamer Jaleel; John D. Owens; Edgar Solomonik; Joel S. Emer; Christopher W. Fletcher (ASPLOS (3), 2023)

Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. - Helen Xu 001; Tao B. Schardl; Michael Pellauer; Joel S. Emer (DCC, 2023)

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). - Toluwanimi O. Odemuyiwa; Hadi Asghari Moghaddam; Michael Pellauer; Kartik Hegde; Po-An Tsai; Neal Clayton Crago; Aamer Jaleel; John D. Owens; Edgar Solomonik; Joel S. Emer; Christopher W. Fletcher (HOPC@SPAA, 2023)

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. - Nandeeka Nayak; Toluwanimi O. Odemuyiwa; Shubham Ugare; Christopher W. Fletcher; Michael Pellauer; Joel S. Emer (MICRO, 2023)

Exploiting Inter-Operation Data Reuse in Scientific Applications using GOGETA. - Raveesh Garg; Michael Pellauer; Sivasankaran Rajamanickam; Tushar Krishna (CoRR, 2023)

Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. - Michael Pellauer; Jason Clemons; Vignesh Balaji; Neal Clayton Crago; Aamer Jaleel; Donghyuk Lee; Mike O'Connor; Anghsuman Parashar; Sean Treichler; Po-An Tsai; Stephen W. Keckler; Joel S. Emer (ACM Trans. Comput. Syst., 2023)

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract). - Nandeeka Nayak; Toluwanimi O. Odemuyiwa; Shubham Ugare; Christopher W. Fletcher; Michael Pellauer; Joel S. Emer (HOPC@SPAA, 2024)

Characterizing the Accuracy-Efficiency Trade-off of Low-rank Decomposition in Language Models. - Chakshu Moar; Faraz Tahmasebi; Michael Pellauer; Hyoukjun Kwon (IISWC, 2024)

FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. - Nandeeka Nayak; Xinrui Wu; Toluwanimi O. Odemuyiwa; Michael Pellauer; Joel S. Emer; Christopher W. Fletcher (MICRO, 2024)

Characterizing the Accuracy - Efficiency Trade-off of Low-rank Decomposition in Language Models. - Chakshu Moar; Michael Pellauer; Hyoukjun Kwon (CoRR, 2024)

ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs. - Nicolás Meseguer; Yifan Sun 002; Michael Pellauer; José L. Abellán; Manuel E. Acacio (GPGPU@PPoPP, 2025)

Cello: Co-Designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor Reuse. - Raveesh Garg; Michael Pellauer; Sivasankaran Rajamanickam; Tushar Krishna (IPDPS, 2025)

HARP: A Taxonomy for Heterogeneous and Hierarchical Processors for Mixed-reuse Workloads. - Raveesh Garg; Michael Pellauer; Tushar Krishna (CoRR, 2025)