An analog DFE for disk drives using a mixed-signal integrator. - Michael Q. Le; Paul J. Hurst; Kenneth C. Dyer (IEEE J. Solid State Circuits, 1999)

An adaptive analog noise-predictive decision-feedback equalizer. - Michael Q. Le; Paul J. Hurst; John P. Keane (IEEE J. Solid State Circuits, 2002)

Analog timing recovery for a noise-predictive decision-feedback equalizer. - John P. Keane; Michael Q. Le; Paul J. Hurst (IEEE J. Solid State Circuits, 2003)

A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration. - Chun-Ying Chen; Michael Q. Le; Kwang Young Kim (IEEE J. Solid State Circuits, 2009)

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS. - Karthik Gopalakrishnan; Alan Ren; Amber Tan; Arash Farhood; Arun Tiruvur; Belal Helal; Chang-Feng Loi; Chris Jiang; Halil Cirit; Irene Quek; Jamal Riani; James Gorecki; et al. (ISSCC, 2016)

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS. - Michael Q. Le; James Gorecki; Jamal Riani; Jorge Pernillo; A. Tan; K. Gopalakrishnan; Belal Helal; Pulkit Khandelwal; Chang-Feng Loi; Irene Quek; P. Wong; Aaron Buchwald (CICC, 2017)

A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET. - Chang-Feng Loi; A. Mellati; Amber Tan; A. Farhoodfar; Arun Tiruvur; Belal Helal; Bob Killips; Farshid Rafiee Rad; Jamal Riani; Jorge Pernillo; J. Sun; J. Wong; et al. (ISSCC, 2019)