Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques. - Andreas Leininger; Martin Fischer 002; Michael Richter 002; Michael Gössel (ITC, 2007)

Accelerated Shift Registers for X-tolerant Test Data Compaction. - Martin Hilscher; Michael Braun; Michael Richter 002; Andreas Leininger; Michael Gössel (ETS, 2008)

New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability. - Michael Richter 002; Klaus Oberländer; Michael Gössel (IOLTS, 2008)

Concurrent checking with split-parity codes. - Michael Richter 002; Michael Gössel (IOLTS, 2009)

X-tolerant Test Data Compaction with Accelerated Shift Registers. - Martin Hilscher; Michael Braun; Michael Richter 002; Andreas Leininger; Michael Gössel (J. Electron. Test., 2009)

High Performance Compaction for Test Responses with Many Unknowns. - Thomas Rabenalt; Michael Richter 002; Michael Gössel (Asian Test Symposium, 2010)

Anwendung nichtlinearer Codes zur Fehlererkennung und -korrektur. - Michael Richter 002 (2011)

Test pin count reduction for NoC-based Test delivery in multicore SOCs. - Michael Richter 002; Krishnendu Chakrabarty (DATE, 2012)

A dynamic programming solution for optimizing test delivery in multicore SOCs. - Mukesh Agrawal 001; Michael Richter 002; Krishnendu Chakrabarty (ITC, 2012)

Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique. - Thomas Rabenalt; Michael Richter 002; Frank Poehl; Michael Gössel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs. - Michael Richter 002; Krishnendu Chakrabarty (IEEE Trans. Computers, 2014)

Test-Delivery Optimization in Manycore SOCs. - Mukesh Agrawal 001; Michael Richter 002; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)