A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

The 48-core SCC Processor: the Programmer's View. - Timothy G. Mattson; Michael Riepen; Thomas Lehnig; Paul Brett; Werner Haas 002; Patrick Kennedy; Jason Howard; Sriram R. Vangal; Nitin Borkar; Gregory Ruhl; Saurabh Dighe (SC, 2010)

RCKMPI - Lightweight MPI Implementation for Intel's Single-chip Cloud Computer (SCC). - Isaías A. Comprés Ureña; Michael Riepen; Michael Konow (EuroMPI, 2011)

SCC: A Flexible Architecture for Many-Core Platform Research. - Matthias Gries; Ulrich Hoffmann; Michael Konow; Michael Riepen (Comput. Sci. Eng., 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

Invasive MPI on Intel's Single-Chip Cloud Computer. - Isaías A. Comprés Ureña; Michael Riepen; Michael Konow; Michael Gerndt (ARCS, 2012)

Connecting the Cloud: Transparent and Flexible Communication for a Cluster of Intel SCCs. - Pablo Reble; Carsten Clauss; Michael Riepen; Stefan Lankes; Thomas Bemmerl (MARC@RWTH, 2012)

Enabling Computation Intensive Applications in Battery-Operated Cyber-Physical Systems. - Hans C. Woithe; William Brozas; Christian Wills; Bharath Pichai; Ulrich Kremer; Mike Eichhorn; Michael Riepen (MARC Symposium, 2012)