Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph. - Yu Bai 004; Abigail Fuentes-Rivera; Michael Riera; Mohammed Alawad; Mingjie Lin (FCCM, 2013)

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph. - Yu Bai 004; Mohammed Alawad; Michael Riera; Mingjie Lin (ReConFig, 2013)

HALO 1.0: A Hardware-agnostic Accelerator Orchestration Framework for Enabling Hardware-agnostic Programming with True Performance Portability for Heterogeneous HPC. - Michael Riera; Erfan Bank Tavakoli; Masudul Hassan Quraishi; Fengbo Ren (CoRR, 2020)

FSCHOL: An OpenCL-based HPC Framework for Accelerating Sparse Cholesky Factorization on FPGAs. - Erfan Bank Tavakoli; Michael Riera; Masudul Hassan Quraishi; Fengbo Ren (SBAC-PAD, 2021)

FLASH 1.0: A Software Framework for Rapid Parallel Deployment and Enhancing Host Code Portability in Heterogeneous Computing. - Michael Riera; Masudul Hassan Quraishi; Erfan Bank Tavakoli; Fengbo Ren (CoRR, 2021)

FSpGEMM: An OpenCL-based HPC Framework for Accelerating General Sparse Matrix-Matrix Multiplication on FPGAs. - Erfan Bank-Tavakoli; Michael Riera; Masudul Hassan Quraishi; Fengbo Ren (CoRR, 2021)

FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs. - Erfan Bank Tavakoli; Michael Riera; Masudul Hassan Quraishi; Fengbo Ren (IEEE Trans. Very Large Scale Integr. Syst., 2024)

SAF: Scalable Acceleration Framework for dynamic and flexible scaling of FPGAs. - Masudul Hassan Quraishi; Michael Riera; Fengbo Ren; Aman Arora 001; Aviral Shrivastava (CoRR, 2025)