A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)

Advancements in at-speed array BIST: multiple improvements. - Kevin W. Gorman; Michael Roberge; Adrian Paparelli; Gary Pomichter; Stephen Sliva; William Corbin (ITC, 2007)

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. - Mark Jacunski; Darren Anand; Robert Busch; John A. Fifield; Matthew Lanahan; Paul Lane; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2010)

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. - Eric Hunt-Schroeder; Darren Anand; John A. Fifield; Mark Jacunski; Michael Roberge; Dale E. Pontius; Kevin Batson; Toshiaki Kirihata (VLSI Circuits, 2018)

Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory. - Eric Hunt-Schroeder; Darren Anand; Edward Hwang; Aaron Cummings; Matthew Deming; Michael Roberge; Michael Ziegerhofer (NATW, 2019)