A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. - Eva Tatschl-Unterberger; Sasan Cyrusian; Michael Ruegg (ISCAS (6), 2005)

A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. - Thomas Toifl; Christian Menolfi; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Robert Reutemann; Michael Ruegg; Martin L. Schmatz; Jonas R. M. Weiss (IEEE J. Solid State Circuits, 2005)

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Martin L. Schmatz (IEEE J. Solid State Circuits, 2006)

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (ISSCC, 2010)

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2010)

A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. - Christian Menolfi; Thomas Toifl; Michael Ruegg; Matthias Braendli; Peter Buchmann; Marcel A. Kossel; Thomas Morf (ISSCC, 2011)

Refactoring towards seams in C++. - Michael Ruegg; Peter Sommerlad (AST, 2012)

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. - Thomas Toifl; Michael Ruegg; Rajesh Inti; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Peter Buchmann; Pier Andrea Francese; Thomas Morf (VLSIC, 2012)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)