The Power PC 601 microprocessor. - Michael C. Becker; Michael S. Allen; Charles R. Moore; John S. Muhich; David P. Tuttle (IEEE Micro, 1993)

Designing the PowerPC 60X bus. - Michael S. Allen; Michael Alexander; Chuck Wright; Joe Chang (IEEE Micro, 1994)

A Pipelined, Weakly Ordered Bus for Multiprocessing Systems. - Michael S. Allen; W. Kurt Lewchuk (COMPCON, 1995)

A high performance bus and cache controller for PowerPC multiprocessing systems. - Michael S. Allen; W. Kurt Lewchuk; J. D. Coddington (ICCD, 1995)

A bidirectional load applicator for the investigation of skin response to mechanical stress. - Joan E. Sanders; Joseph L. Garbini; Jamie M. Leschen; Michael S. Allen; Jens E. Jorgensen (IEEE Trans. Biomed. Eng., 1997)

A Dialogue Process for Choosing Value-Creating Strategies. - Samuel E. Bodily; Michael S. Allen (Interfaces, 1999)

A 333-MHz dual-MAC DSP architecture for next-generation wireless applications. - Ravi K. Kolagotla; José Fridman; Marc M. Hoffman; William C. Anderson; Bradley C. Aldrich; David B. Witt; Michael S. Allen; Randy R. Dunton; Lawrence A. Booth Jr. (ICASSP, 2001)

High performance dual-MAC DSP architecture. - Ravi K. Kolagotla; José Fridman; Bradley C. Aldrich; Marc M. Hoffman; William C. Anderson; Michael S. Allen; David B. Witt; Randy R. Dunton; Lawrence A. Booth Jr. (IEEE Signal Process. Mag., 2002)

Cached memory performance characterization of a wireless digital baseband processor. - Srikanth Kannan; Michael S. Allen; José Fridman (ICASSP (5), 2004)

The New York City Off-Hour Delivery Program: A Business and Community-Friendly Sustainability Program. - José Holguín-Veras; Stacey Hodge; Jeffrey Wojtowicz; Caesar Singh; Cara Wang; Miguel Jaller; Felipe Aros-Vera; Kaan Ozbay; Andrew Weeks; Michael Replogle; Charles Ukegbu; Jeff Ban; et al. (Interfaces, 2018)