Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology. - Douglas C. Bossen; Alongkorn Kitamorn; Kevin Reick; Michael S. Floyd (IBM J. Res. Dev., 2002)

Design and implementation of the POWER5 microprocessor. - Joachim G. Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam G. Chu; Donald W. Plass; James Dawson; Paul Muench; Larry Powell; Michael S. Floyd; Balaram Sinharoy; Mike Lee; et al. (DAC, 2004)

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. - Alan J. Drake; Robert M. Senger; Harmander Deogun; Gary D. Carpenter; Soraya Ghiasi; Tuyet Nguyen; Norman K. James; Michael S. Floyd; Vikas Pokala (ISSCC, 2007)

System power management support in the IBM POWER6 microprocessor. - Michael S. Floyd; Soraya Ghiasi; Tom W. Keller; Karthick Rajamani; Freeman L. Rawson III; Juan C. Rubio; Malcolm S. Ware (IBM J. Res. Dev., 2007)

EnergyScale for IBM POWER6 microprocessor-based systems. - Hye-Young McCreary; Martha A. Broyles; Michael S. Floyd; Andrew J. Geissler; Steven P. Hartman; Freeman L. Rawson III; Todd J. Rosedahl; Juan C. Rubio; Malcolm S. Ware (IBM J. Res. Dev., 2007)

Fault-Tolerant Design of the IBM Power6 Microprocessor. - Kevin Reick; Pia N. Sanda; Scott B. Swaney; Jeffrey W. Kellington; Michael J. Mack; Michael S. Floyd; Daniel Henderson (IEEE Micro, 2008)

Adaptive energy management features of the POWER7TM processor. - Michael S. Floyd; Bishop Brock; Malcolm S. Ware; Karthick Rajamani; Alan J. Drake; Charles Lefurgy; Lorena Pesantez (Hot Chips Symposium, 2010)

Architecting for power management: The IBM POWER7TM approach. - Malcolm S. Ware; Karthick Rajamani; Michael S. Floyd; Bishop Brock; Juan C. Rubio; Freeman L. Rawson III; John B. Carter (HPCA, 2010)

Power7: IBM's Next-Generation Server Processor. - Ronald N. Kalla; Balaram Sinharoy; William J. Starke; Michael S. Floyd (IEEE Micro, 2010)

Active management of timing guardband to save energy in POWER7. - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter (MICRO, 2011)

Adaptive energy-management features of the IBM POWER7 chip. - Michael S. Floyd; Malcolm Allen-Ware; Karthick Rajamani; Tilman Gloekler; Bishop Brock; Pradip Bose; Alper Buyuktosunoglu; Juan C. Rubio; Birgit Schubert; Bruno Spruth; José A. Tierno; Lorena Pesantez (IBM J. Res. Dev., 2011)

Introducing the Adaptive Energy Management Features of the Power7 Chip. - Michael S. Floyd; Malcolm Allen-Ware; Karthick Rajamani; Bishop Brock; Charles Lefurgy; Alan J. Drake; Lorena Pesantez; Tilman Gloekler; José A. Tierno; Pradip Bose; Alper Buyuktosunoglu (IEEE Micro, 2011)

Accurate Fine-Grained Processor Power Proxies. - Wei Huang 004; Charles Lefurgy; William Kuk; Alper Buyuktosunoglu; Michael S. Floyd; Karthick Rajamani; Malcolm Allen-Ware; Bishop Brock (MICRO, 2012)

Voltage droop reduction using throttling controlled by timing margin feedback. - Michael S. Floyd; Alan J. Drake; Robert W. Berry; Harold Chase; Richard L. Willaman; Jarom Peña (VLSIC, 2012)

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. - Alan J. Drake; Michael S. Floyd; Richard L. Willaman; Derek J. Hathaway; Joshua Hernandez; Crystal Soja; Marshall D. Tiner; Gary D. Carpenter; Robert M. Senger (ISLPED, 2013)

Virtual Power Management simulation framework for computer systems. - Bishop Brock; Srinivasan Ramani; Ken Vu; Heather Hanson; Michael S. Floyd (ISPASS, 2013)

Runtime power reduction capability of the IBM POWER7+ chip. - Michael S. Floyd; Alan J. Drake; Nicole S. Schwartz; Robert W. Berry; Charles Lefurgy; Malcolm S. Ware; Karthick Rajamani; Victor V. Zyuban; Richard L. Willaman; Ruby M. Zgabay (IBM J. Res. Dev., 2013)

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter; Robert W. Berry (IEEE Micro, 2013)

Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. - Yazhou Zu; Charles R. Lefurgy; Jingwen Leng; Matthew Halpern; Michael S. Floyd; Vijay Janapa Reddi (MICRO, 2015)

Debugging post-silicon fails in the IBM POWER8 bring-up lab. - Manoj Dusanapudi; S. Fields; Michael S. Floyd; Guy L. Guthrie; Ronald N. Kalla; Shakti Kapoor; Larry S. Leitner; Charles F. Marino; Joseph McGill; Amir Nahir; Kevin Reick; H. Shen; et al. (IBM J. Res. Dev., 2015)

Robust power management in the IBM z13. - Tobias Webel; Preetham M. Lobo; Ramon Bertran; Gerard Salem; Malcolm Allen-Ware; Richard F. Rizzolo; Sean M. Carey; Thomas Strach; Alper Buyuktosunoglu; Charles Lefurgy; Pradip Bose; Ricardo Nigaglioni; et al. (IBM J. Res. Dev., 2015)

26.2 Power supply noise in a 22nm z13™ microprocessor. - Pierce I-Jen Chuang; Christos Vezyrtzis; Divya Pathak; Richard F. Rizzolo; Tobias Webel; Thomas Strach; Otto A. Torreiter; Preetham Lobo; Alper Buyuktosunoglu; Ramon Bertran; Michael S. Floyd; Malcolm S. Ware; et al. (ISSCC, 2017)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. - Christos Vezyrtzis; Thomas Strach; Pierce I-Jen Chuang; Preetham Lobo; Richard F. Rizzolo; Tobias Webel; Pawel Owczarczyk; Alper Buyuktosunoglu; Ramon Bertran; David T. Hui; Susan M. Eickhoff; Michael S. Floyd; et al. (ISSCC, 2018)

IBM POWER9 processor and system features for computing in the cognitive era. - L. Baba Arimilli; Bart Blaner; Ben C. Drerup; Charles F. Marino; Derek Williams; Eric N. Lais; Francesco A. Campisano; Guy L. Guthrie; Michael S. Floyd; Ross Leavens; Scot M. Willenborg; Ronald N. Kalla; et al. (IBM J. Res. Dev., 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)