A new architectural-level fault simulation using propagation prediction of grouped fault-effects. - Michael S. Hsiao; Janak H. Patel (ICCD, 1995)

Alternating Strategies for Sequential Circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1996)

Automatic test generation using genetically-engineered distinguishing sequences. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

Sequential circuit test generation using dynamic state traversal. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1997)

Partial Scan beyond Cycle Cutting. - Gurjeet S. Saund; Michael S. Hsiao; Janak H. Patel (FTCS, 1997)

Effects of delay models on peak power estimation of VLSI sequential circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1997)

K2: an estimator for peak sustainable power of VLSI circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ISLPED, 1997)

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. - Dilip Krishnaswamy; Michael S. Hsiao; Vikram Saxena; Elizabeth M. Rudnick; Janak H. Patel; Prithviraj Banerjee (VLSI Design, 1997)

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1997)

Sequential Circuit Test Generation Using Genetic Techniques - Michael S. Hsiao (1997)

Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. - Michael S. Hsiao; Srimat T. Chakradhar (Asian Test Symposium, 1998)

State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. - Michael S. Hsiao; Srimat T. Chakradhar (DATE, 1998)

A fast, accurate, and non-statistical method for fault coverage estimation. - Michael S. Hsiao (ICCAD, 1998)

Partial Scan Selection Based on Dynamic Reachability and Observability Information. - Michael S. Hsiao; Gurjeet S. Saund; Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1998)

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. - Michael S. Hsiao (DATE, 1999)

An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. - Sandhya Seshadri; Michael S. Hsiao (ITC, 1999)

Instruction Scheduling in the Presence of Java's Runtime Exceptions. - Matthew Arnold; Michael S. Hsiao; Ulrich Kremer; Barbara G. Ryder (LCPC, 1999)

On the Evaluation of Arbitrary Defect Coverage of Test Sets. - Ankur Jain; Michael S. Hsiao; Vamsi Boppana; Masahiro Fujita (VTS, 1999)

Partial Scan Using Multi-Hop State Reachability Analysis. - Sameer Sharma; Michael S. Hsiao (VTS, 1999)

On Non-Statistical Techniques for Fast Fault Coverage Estimation. - Michael S. Hsiao (J. Electron. Test., 1999)

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Computers, 1999)

Compaction-based test generation using state and fault information. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (Asian Test Symposium, 2000)

Embedded core testing using genetic algorithms. - Ruofan Xu; Michael S. Hsiao (Asian Test Symposium, 2000)

Multi-Node Static Logic Implications for Redundancy Identification. - Kabir Gulrajani; Michael S. Hsiao (DATE, 2000)

Formal operator testability methods for behavioral-level DFT using value ranges. - Sandhya Seshadri; Michael S. Hsiao (HLDVT, 2000)

Compiler-Directed Dynamic Frequency and Voltage Scheduling. - Chung-Hsing Hsu; Ulrich Kremer; Michael S. Hsiao (PACS, 2000)

Testing, Verification, and Diagnosis in the Presence of Unknowns. - Ankur Jain; Vamsi Boppana; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Michael S. Hsiao (VTS, 2000)

Test Set Compaction Using Relaxed Subsequence Removal. - Michael S. Hsiao; Srimat T. Chakradhar (J. Electron. Test., 2000)

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. - Michael S. Hsiao; Srimat T. Chakradhar (J. Electron. Test., 2000)

Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. - Sandhya Seshadri; Michael S. Hsiao (J. Electron. Test., 2000)

Dynamic state traversal for sequential circuit test generation. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ACM Trans. Design Autom. Electr. Syst., 2000)

Peak power estimation of VLSI circuits: new peak power measures. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Efficient spectral techniques for sequential ATPG. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (DATE, 2001)

Practical use of sequential ATPG for model checking: going the extra mile does pay off. - Michael S. Hsiao; Jawahar Jain (HLDVT, 2001)

Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors. - Chung-Hsing Hsu; Ulrich Kremer; Michael S. Hsiao (ISLPED, 2001)

Fast, flexible, cycle-accurate energy estimation. - Phillip Stanley-Marbell; Michael S. Hsiao (ISLPED, 2001)

On efficient error diagnosis of digital circuits. - Nandini Sridhar; Michael S. Hsiao (ITC, 2001)

Error Diagnosis of Sequential Circuits Using Region-Based Mode. - Anand L. D'Souza; Michael S. Hsiao (VLSI Design, 2001)

Accurate Power Macro-modeling Techniques for Complex RTL Circuits. - Nachiketh R. Potlapally; Michael S. Hsiao; Anand Raghunathan; Ganesh Lakshminarayana; Srimat T. Chakradhar (VLSI Design, 2001)

Combination of Structural and State Analysis for Partial Scan. - Sameer Sharma; Michael S. Hsiao (VLSI Design, 2001)

Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (VTS, 2001)

Exploring the Interaction between Java?s Implicitly Thrown Exceptions and Instruction Scheduling. - Matthew Arnold; Michael S. Hsiao; Ulrich Kremer; Barbara G. Ryder (Int. J. Parallel Program., 2001)

Effective safety property checking using simulation-based sequential ATPG. - Shuo Sheng; Koichiro Takayama; Michael S. Hsiao (DAC, 2002)

Maximizing Impossibilities for Untestable Fault Identification. - Michael S. Hsiao (DATE, 2002)

Novel ATPG algorithms for transition faults. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ETW, 2002)

Characteristic faults and spectral information for logic BIST. - Xiaoding Chen; Michael S. Hsiao (ICCAD, 2002)

Techniques to Reduce Data Volume and Application Time for Transition Test. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ITC, 2002)

Improving Sequential ATPG Using SAT Methods. - Mukul R. Prasad; Michael S. Hsiao; Jawahar Jain (IWLS, 2002)

Reducing Power Consumption by Utilizing Retransmission in Short Range Wireless Network. - Yufeng Zhao; Michael S. Hsiao (LCN, 2002)

A Hardware Architecture for Dynamic Performance and Energy Adaptation. - Phillip Stanley-Marbell; Michael S. Hsiao; Ulrich Kremer (PACS, 2002)

Spectrum-Based BIST in Complex SOCs. - Ganapathy Kasturirangan; Michael S. Hsiao (VTS, 2002)

Efficient Sequential Test Generation Based on Logic Simulation. - Shuo Sheng; Michael S. Hsiao (IEEE Des. Test Comput., 2002)

State and Fault Information for Compaction-Based Test Generation. - Ashish Giani; Shuo Sheng; Michael S. Hsiao; Vishwani D. Agrawal (J. Electron. Test., 2002)

Behavioral-Level DFT via Formal Operator Testability Measures. - Sandhya Seshadri; Michael S. Hsiao (J. Electron. Test., 2002)

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits. - Michael S. Hsiao (VLSI Design, 2002)

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. - Liang Zhang 012; Michael S. Hsiao; Indradeep Ghosh (Asian Test Symposium, 2003)

Efficient Preimage Computation Using A Novel Success-Driven ATPG. - Shuo Sheng; Michael S. Hsiao (DATE, 2003)

A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. - Manan Syal; Michael S. Hsiao (DATE, 2003)

Constrained ATPG for Broadside Transition Testing. - Xiao Liu 010; Michael S. Hsiao (DFT, 2003)

Enhancing SAT-based equivalence checking with static logic implications. - Rajat Arora; Michael S. Hsiao (HLDVT, 2003)

ATPG-based preimage computation: efficient search space pruning with ZBDD. - Kameshwar Chandrasekar; Michael S. Hsiao (HLDVT, 2003)

High Quality ATPG for Delay Defects. - Puneet Gupta; Michael S. Hsiao (ITC, 2003)

Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. - Qingwei Wu; Michael S. Hsiao (ITC, 2003)

Efficient Sequential ATPG for Functional RTL Circuits. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (ITC, 2003)

Energy-Efficient Logic BIST Based on State Correlation Analysis. - Xiaoding Chen; Michael S. Hsiao (VTS, 2003)

Efficient Implication - Based Untestable Bridge Fault Identifier. - Manan Syal; Michael S. Hsiao; Kiran B. Doreswamy; Sreejit Chakravarty (VTS, 2003)

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (J. Electron. Test., 2003)

A Novel SAT All-Solutions Solver for Efficient Preimage Computation. - Bin Li; Michael S. Hsiao; Shuo Sheng (DATE, 2004)

CNF formula simplification using implication reasoning. - Rajat Arora; Michael S. Hsiao (HLDVT, 2004)

On identifying functionally untestable transition faults. - Xiao Liu 010; Michael S. Hsiao (HLDVT, 2004)

Incremental deductive & inductive reasoning for SAT-based bounded model checking. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao (ICCAD, 2004)

Decision Selection and Learning for an All-Solutions ATPG Engine. - Kameshwar Chandrasekar; Michael S. Hsiao (ITC, 2004)

ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. - Puneet Gupta; Michael S. Hsiao (ITC, 2004)

Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. - Manan Syal; Michael S. Hsiao; Sreejit Chakravarty (ITC, 2004)

State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. - Qingwei Wu; Michael S. Hsiao (ITC, 2004)

Denial-of-Service Attacks on Battery-powered Mobile Computers. - Thomas L. Martin; Michael S. Hsiao; Dong S. Ha 001; Jayan Krishnaswami (PerCom, 2004)

Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications. - Rajat Arora; Michael S. Hsiao (VLSI Design, 2004)

Can SAT be used to Improve Sequential ATPG Methods? - Mukul R. Prasad; Michael S. Hsiao; Jawahar Jain (VLSI Design, 2004)

Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments. - Manan Syal; Michael S. Hsiao (VLSI Design, 2004)

Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. - Qingwei Wu; Michael S. Hsiao (VTS, 2004)

Success-Driven Learning in ATPG for Preimage Computation. - Shuo Sheng; Michael S. Hsiao (IEEE Des. Test Comput., 2004)

Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking. - Rajat Arora; Michael S. Hsiao (J. Univers. Comput. Sci., 2004)

Untestable Multi-Cycle Path Delay Faults in Industrial Designs. - Manan Syal; Michael S. Hsiao; Suriyaprakash Natarajan; Sreejit Chakravarty (Asian Test Symposium, 2005)

Interleaved Invariant Checking with Dynamic Abstraction. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao (CHARME, 2005)

Dynamic abstraction using SAT-based BMC. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao; Thomas Sidle (DAC, 2005)

Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. - Kameshwar Chandrasekar; Michael S. Hsiao (DATE, 2005)

Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing. - Shrirang M. Yardi; Michael S. Hsiao; Thomas L. Martin; Dong S. Ha 001 (DATE, 2005)

Forward image computation with backtracing ATPG and incremental state-set construction. - Kameshwar Chandrasekar; Michael S. Hsiao (ACM Great Lakes Symposium on VLSI, 2005)

An effective and efficient ATPG-based combinational equivalence checker. - Ronald P. Lajaunie; Michael S. Hsiao (ACM Great Lakes Symposium on VLSI, 2005)

Untestable fault identification through enhanced necessary value assignments. - Vishnu C. Vimjam; Manan Syal; Michael S. Hsiao (ACM Great Lakes Symposium on VLSI, 2005)

VERISEC: verifying equivalence of sequential circuits using SAT. - Manan Syal; Michael S. Hsiao (HLDVT, 2005)

Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking. - Vishnu C. Vimjam; Michael S. Hsiao (HLDVT, 2005)

State Set Management for SAT-based Unbounded Model Checking. - Kameshwar Chandrasekar; Michael S. Hsiao (ICCD, 2005)

Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults. - Manan Syal; Rajat Arora; Michael S. Hsiao (ICCD, 2005)

A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management. - Shrirang M. Yardi; Karthik Channakeshava; Michael S. Hsiao; Thomas L. Martin; Dong S. Ha 001 (ICCD, 2005)

Region-level approximate computation reuse for power reduction in multimedia applications. - Xueqi Cheng; Michael S. Hsiao (ISLPED, 2005)

Towards an Intrusion Detection System for Battery Exhaustion Attacks on Mobile Computing Devices. - Daniel C. Nash; Thomas L. Martin; Dong S. Ha 001; Michael S. Hsiao (PerCom Workshops, 2005)

Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. - Kameshwar Chandrasekar; Michael S. Hsiao (VLSI Design, 2005)

A Novel Transition Fault ATPG That Reduces Yield Loss. - Xiao Liu 010; Michael S. Hsiao (IEEE Des. Test Comput., 2005)

Error Diagnosis of Sequential Circuits Using Region-Based Model. - Anand L. D'Souza; Michael S. Hsiao (J. Electron. Test., 2005)

Efficient techniques for transition testing. - Xiao Liu 010; Michael S. Hsiao; Sreejit Chakravarty; Paul J. Thadikaran (ACM Trans. Design Autom. Electr. Syst., 2005)

Fast illegal state identification for improving SAT-based induction. - Vishnu C. Vimjam; Michael S. Hsiao (DAC, 2006)

Mining global constraints for improving bounded sequential equivalence checking. - Weixin Wu; Michael S. Hsiao (DAC, 2006)

Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. - Kameshwar Chandrasekar; Michael S. Hsiao (ICCD, 2006)

Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation. - Xiaoding Chen; Michael S. Hsiao (ITC, 2006)

A Study of Implication Based Pseudo Functional Testing. - Manan Syal; Kameshwar Chandrasekar; Vishnu C. Vimjam; Michael S. Hsiao; Yi-Shing Chang; Sreejit Chakravarty (ITC, 2006)

Efficient Fault Collapsing via Generalized Dominance Relations. - Vishnu C. Vimjam; Michael S. Hsiao (VTS, 2006)

Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. - Xiaoding Chen; Michael S. Hsiao (IEEE Trans. Computers, 2006)

A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal. - Qingwei Wu; Michael S. Hsiao (IEEE Trans. Computers, 2006)

New techniques for untestable fault identification in sequential circuits. - Manan Syal; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation. - Qingwei Wu; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Parents and the Internet: Privacy Awareness, Practices and Control. - Michael S. Hsiao; France Bélanger; Janine S. Hiller; Payal Aggarwal; Karthik Channakeshava; Kaigui Bian; Jung-Min Park 001 (AMCIS, 2007)

Mining Sequential Constraints for Pseudo-Functional Testing. - Weixin Wu; Michael S. Hsiao (ATS, 2007)

A new hybrid solution to boost SAT solver performance. - Lei Fang 002; Michael S. Hsiao (DATE, 2007)

Bounded model checking of embedded software in wireless cognitive radio systems. - Nannan He; Michael S. Hsiao (ICCD, 2007)

Efficient power droop aware delay fault testing. - Bin Li; Lei Fang 002; Michael S. Hsiao (ITC, 2007)

Mining-guided state justification with partitioned navigation tracks. - Ankur Parikh; Weixin Wu; Michael S. Hsiao (ITC, 2007)

Integrating Validation and Verification in the Digital Design Curriculum. - Shrirang M. Yardi; Michael S. Hsiao (MSE, 2007)

Explicit Safety Property Strengthening in SAT-based Induction. - Vishnu C. Vimjam; Michael S. Hsiao (VLSI Design, 2007)

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. - Vishnu C. Vimjam; M. Enamul Amyeen; Ruifeng Guo; Srikanth Venkataraman; Michael S. Hsiao; Kai Yang (VTS, 2007)

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. - Xiaoding Chen; Michael S. Hsiao (IEEE Trans. Very Large Scale Integr. Syst., 2007)

On Providing Automatic Parental Consent over Information Collection from Children. - Karthik Channakeshava; Kaigui Bian; Michael S. Hsiao; Jung-Min Park 001; Robert E. Crossler; France Bélanger; Payal Aggarwal; Janine S. Hiller (Security and Management, 2008)

Simulation-Directed Invariant Mining for Software Verification. - Xueqi Cheng; Michael S. Hsiao (DATE, 2008)

A Fast Approximation Algorithm for MIN-ONE SAT. - Lei Fang 002; Michael S. Hsiao (DATE, 2008)

Efficient Design Validation Based on Cultural Algorithms. - Weixin Wu; Michael S. Hsiao (DATE, 2008)

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. - Shianling Wu; Laung-Terng Wang; Zhigang Jiang; Jiayong Song; Boryau Sheu; Xiaoqing Wen; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Ravi Apte (DFT, 2008)

Guided test generation for isolation and detection of embedded trojans in ics. - Mainak Banga; Maheshwar Chandrasekar; Lei Fang 002; Michael S. Hsiao (ACM Great Lakes Symposium on VLSI, 2008)

SAT-based equivalence checking of threshold logic designs for nanotechnologies. - Yexin Zheng; Michael S. Hsiao; Chao Huang (ACM Great Lakes Symposium on VLSI, 2008)

On dynamic switching of navigation for semi-formal design validation. - Ankur Parikh; Michael S. Hsiao (HLDVT, 2008)

A Region Based Approach for the Identification of Hardware Trojans. - Mainak Banga; Michael S. Hsiao (HOST, 2008)

Ant Colony Optimization directed program abstraction for software bounded model checking. - Xueqi Cheng; Michael S. Hsiao (ICCD, 2008)

Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads. - Shrirang M. Yardi; Michael S. Hsiao (ICCD, 2008)

SAT-based State Justification with Adaptive Mining of Invariants. - Weixin Wu; Michael S. Hsiao (ITC, 2008)

Bilateral Testing of Nano-scale Fault-Tolerant Circuits. - Lei Fang 002; Michael S. Hsiao (J. Electron. Test., 2008)

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. - Hong-Sik Kim; Sungho Kang 001; Michael S. Hsiao (J. Electron. Test., 2008)

Boosting SAT Solver Performance via a New Hybrid Approach. - Lei Fang 002; Michael S. Hsiao (J. Satisf. Boolean Model. Comput., 2008)

Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. - Weixin Wu; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Introduction to special section on high-level design, validation, and test. - Michael S. Hsiao; Robert B. Jones (ACM Trans. Design Autom. Electr. Syst., 2008)

Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time. - Michael S. Hsiao; Mainak Banga (Asian Test Symposium, 2009)

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug. - Sandesh Prabhakar; Michael S. Hsiao (Asian Test Symposium, 2009)

An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification. - Nannan He; Michael S. Hsiao (DATE, 2009)

Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility. - Maheshwar Chandrasekar; Michael S. Hsiao (HLDVT, 2009)

VITAMIN: Voltage Inversion Technique to Ascertain Malicious Insertions in ICs. - Mainak Banga; Michael S. Hsiao (HOST, 2009)

Fast circuit topology based method to configure the scan chains in Illinois Scan architecture. - Swapneel Donglikar; Mainak Banga; Maheshwar Chandrasekar; Michael S. Hsiao (ITC, 2009)

An ant colony optimization technique for abstraction-guided state justification. - Min Li 013; Michael S. Hsiao (ITC, 2009)

Evaluation of Online Resources in Assisting Phishing Detection. - Kaigui Bian; Jung-Min Park 001; Michael S. Hsiao; France Bélanger; Janine S. Hiller (SAINT, 2009)

A Novel Sustained Vector Technique for the Detection of Hardware Trojans. - Mainak Banga; Michael S. Hsiao (VLSI Design, 2009)

Cognitive Radio and Networking Research at Virginia Tech. - Allen B. MacKenzie; Jeffrey H. Reed; Peter M. Athanas; Charles W. Bostian; R. Michael Buehrer; Luiz A. DaSilva; Steven W. Ellingson; Y. Thomas Hou 001; Michael S. Hsiao; Jung-Min Park 001; Cameron D. Patterson; Sanjay Raman; et al. (Proc. IEEE, 2009)

Mining Complex Boolean Expressions for Sequential Equivalence Checking. - Neha Goel; Michael S. Hsiao; Naren Ramakrishnan; Mohammed J. Zaki (Asian Test Symposium, 2010)

Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. - Saparya Krishnamoorthy; Michael S. Hsiao; Loganathan Lingappan (Asian Test Symposium, 2010)

FSimGP^2: An Efficient Fault Simulator with GPGPU. - Min Li 013; Michael S. Hsiao (Asian Test Symposium, 2010)

DFT + DFD: An Integrated Method for Design for Testability and Diagnosability. - Nikhil P. Rahagude; Maheshwar Chandrasekar; Michael S. Hsiao (Asian Test Symposium, 2010)

Reversible logic synthesis through ant colony optimization. - Min Li 013; Yexin Zheng; Michael S. Hsiao; Chao Huang (DATE, 2010)

Trusted RTL: Trojan Detection Methodology in Pre-silicon Designs. - Mainak Banga; Michael S. Hsiao (HOST, 2010)

Multiplexed trace signal selection using non-trivial implication-based correlation. - Sandesh Prabhakar; Michael S. Hsiao (ISQED, 2010)

Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation. - Maheshwar Chandrasekar; Nikhil P. Rahagude; Michael S. Hsiao (J. Electron. Test., 2010)

An Efficient 2-Phase Strategy to Achieve High Branch Coverage. - Sarvesh Prabhu; Michael S. Hsiao; Saparya Krishnamoorthy; Loganathan Lingappan; Vijay Gangaram; Jim Grundy (Asian Test Symposium, 2011)

Design-for-test methodology for non-scan at-speed testing. - Mainak Banga; Nikhil P. Rahagude; Michael S. Hsiao (DATE, 2011)

Experiment and Analysis Services in a Fingerprint Digital Library for Collaborative Research. - Sung Hee Park; Jonathan Leidig; Lin Tzy Li; Edward A. Fox; Nathan J. Short; Kevin E. Hoyle; A. Lynn Abbott; Michael S. Hsiao (TPDL, 2011)

High-Performance Diagnostic Fault Simulation on GPUs. - Min Li 013; Michael S. Hsiao (ETS, 2011)

Sufficiency-based filtering of invariants for Sequential Equivalence Checking. - Wei Hu; Huy Nguyen; Michael S. Hsiao (HLDVT, 2011)

Utilizing GPGPUs for design validation with a modified Ant Colony Optimization. - Min Li 013; Kelson Gent; Michael S. Hsiao (HLDVT, 2011)

ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs. - Mainak Banga; Michael S. Hsiao (HOST, 2011)

A Bayesian approach to fingerprint minutia localization and quality assessment using adaptable templates. - Nathan J. Short; A. Lynn Abbott; Michael S. Hsiao; Edward A. Fox (IJCB, 2011)

Minutiae + friction ridges = triplet-based features for determining sufficiency in fingerprints. - Kevin E. Hoyle; Nathan J. Short; Michael S. Hsiao; A. Lynn Abbott; Edward A. Fox (ICDP, 2011)

Latent fingerprint segmentation using ridge template correlation. - Nathan J. Short; Michael S. Hsiao; A. Lynn Abbott; Edward A. Fox (ICDP, 2011)

A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation. - Maheshwar Chandrasekar; Michael S. Hsiao (VLSI Design, 2011)

Fault Collapsing Using a Novel Extensibility Relation. - Maheshwar Chandrasekar; Michael S. Hsiao (VLSI Design, 2011)

Trace Buffer-Based Silicon Debug with Lossless Compression. - Sandesh Prabhakar; Rajamani Sethuram; Michael S. Hsiao (VLSI Design, 2011)

Strategies for scalable symbolic execution-driven test generation for programs. - Saparya Krishnamoorthy; Michael S. Hsiao; Loganathan Lingappan (Sci. China Inf. Sci., 2011)

3-D Parallel Fault Simulation With GPGPU. - Min Li 013; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Robust feature extraction in fingerprint images using ridge model tracking. - Nathaniel J. Short; A. Lynn Abbott; Michael S. Hsiao; Edward A. Fox (BTAS, 2012)

Temporal analysis of fingerprint impressions. - Nathaniel J. Short; A. Lynn Abbott; Michael S. Hsiao; Edward A. Fox (BTAS, 2012)

A scan pattern debugger for partial scan industrial designs. - Kameshwar Chandrasekar; Supratik K. Misra; Sanjay Sengupta; Michael S. Hsiao (DATE, 2012)

RAG: An efficient reliability analysis of logic circuits on graphics processing units. - Min Li 013; Michael S. Hsiao (DATE, 2012)

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies. - Huy Nguyen; Michael S. Hsiao (HLDVT, 2012)

Design validation of RTL circuits using evolutionary swarm intelligence. - Min Li 013; Kelson Gent; Michael S. Hsiao (ITC, 2012)

A Novel SMT-Based Technique for LFSR Reseeding. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (VLSI Design, 2012)

A SMT-based diagnostic test generation method for combinational circuits. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (VTS, 2012)

Reducing descriptor measurement error through Bayesian estimation of fingerprint minutia location and direction. - Nathan J. Short; A. Lynn Abbott; Michael S. Hsiao; Edward A. Fox (IET Biom., 2012)

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Wen-Ben Jone; Michael S. Hsiao; Fangfang Li; James Chien-Mo Li; Jiun-Lang Huang (ACM Trans. Design Autom. Electr. Syst., 2012)

Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking. - Kelson Gent; Michael S. Hsiao (Asian Test Symposium, 2013)

Interlocking obfuscation for anti-tamper hardware. - Avinash R. Desai; Michael S. Hsiao; Chao Wang 001; Leyla Nazhandali; T. Simin Hall (CSIIRW, 2013)

LFSR seed computation and reduction using SMT-based fault-chaining. - Dhrumeel Bakshi; Michael S. Hsiao (DATE, 2013)

A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms. - Mahmoud Elbayoumi; Michael S. Hsiao; Mustafa Y. ElNainay (DATE, 2013)

Test generation for circuits with embedded memories using SMT. - Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan; Vijay Gangaram (ETS, 2013)

Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract. - Mahmoud Elbayoumi; Michael S. Hsiao; Mustafa Y. ElNainay (ACM Great Lakes Symposium on VLSI, 2013)

A novel statistical and circuit-based technique for counterfeit detection in existing ICs. - Rashmi Moudgil; Dinesh Ganta; Leyla Nazhandali; Michael S. Hsiao; Chao Wang 001; T. Simin Hall (ACM Great Lakes Symposium on VLSI, 2013)

Selecting critical implications with set-covering formulation for SAT-based Bounded Model Checking. - Mahmoud Elbayoumi; Michael S. Hsiao; Mustafa Y. ElNainay (ICCD, 2013)

POCKET: A tool for protecting children's privacy online. - France Bélanger; Robert E. Crossler; Janine S. Hiller; Jung-Min Park 001; Michael S. Hsiao (Decis. Support Syst., 2013)

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. - Swarup Bhunia; Miron Abramovici; Dakshi Agrawal; Paul Bradley; Michael S. Hsiao; Jim Plusquellic; Mohammad Tehranipoor (IEEE Des. Test, 2013)

Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence. - Kelson Gent; Michael S. Hsiao (ATS, 2014)

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis. - Mahmoud Elbayoumi; Mihir Choudhury; Victor N. Kravets; Andrew Sullivan; Michael S. Hsiao; Mustafa Y. ElNainay (DAC, 2014)

GPU-based timing-aware test generation for small delay defects. - Kuan-Yu Liao; Po-Juei Chen; Ang-Feng Lin; James Chien-Mo Li; Michael S. Hsiao; Laung-Terng Wang (ETS, 2014)

Property-checking based LBIST for improved diagnosability. - Sarvesh Prabhu; Vineeth V. Acharya; Sharad Bagri; Michael S. Hsiao (ETS, 2014)

A diagnosis-friendly LBIST architecture with property checking. - Sarvesh Prabhu; Vineeth V. Acharya; Sharad Bagri; Michael S. Hsiao (ITC, 2014)

Hardware Trojan Attacks: Threat Analysis and Countermeasures. - Swarup Bhunia; Michael S. Hsiao; Mainak Banga; Seetharam Narasimhan (Proc. IEEE, 2014)

Branch guided functional test generation at the RTL. - Vineeth V. Acharya; Sharad Bagri; Michael S. Hsiao (ETS, 2015)

SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships. - Prateek Puri; Michael S. Hsiao (ICCD, 2015)

Signal domain based reachability analysis in RTL circuits. - Sharad Bagri; Kelson Gent; Michael S. Hsiao (ISQED, 2015)

Novel SAT-based invariant-directed low-power synthesis. - Mahmoud Elbayoumi; Michael S. Hsiao; Mustafa ElNainay (ISQED, 2015)

Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization. - Prateek Puri; Michael S. Hsiao (ISVLSI, 2015)

Information-theoretic and statistical methods of failure log selection for improved diagnosis. - Sarmad Tanwir; Sarvesh Prabhu; Michael S. Hsiao; Loganathan Lingappan (ITC, 2015)

Abstraction-based relation mining for functional test generation. - Kelson Gent; Michael S. Hsiao (VTS, 2015)

Dynamic partitioning strategy to enhance symbolic execution. - Brendan A. Marcellino; Michael S. Hsiao (DATE, 2016)

Hardware-in-the-loop model-less diagnostic test generation. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (HLDVT, 2016)

Fast Multi-level Test Generation at the RTL. - Kelson Gent; Michael S. Hsiao (ISVLSI, 2016)

A control path aware metric for grading functional test vectors. - Kelson Gent; Michael S. Hsiao (LATS, 2016)

A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (ACM Great Lakes Symposium on VLSI, 2017)

Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance. - Sonal Pinto; Michael S. Hsiao (ICCD, 2017)

RTL functional test generation using factored concolic execution. - Sonal Pinto; Michael S. Hsiao (ITC, 2017)

A framework for fast test generation at the RTL. - Kelson Gent; Akash Agrawal; Michael S. Hsiao (VTS, 2017)

A Natural Language Programming Application for Lego Mindstorms EV3. - Yue Zhan; Michael S. Hsiao (AIVR, 2018)

Automated Program Synthesis from Object-Oriented Natural Language for Computer Games. - Michael S. Hsiao (CNL, 2018)

Optimization of Mutant Space for RTL Test Generation. - Kunal Bansal; Michael S. Hsiao (ICCD, 2018)

An online framework for diagnosis of multiple defects in scan chains. - Sarmad Tanwir; Michael S. Hsiao; Loganathan Lingappan (ISQED, 2018)

Fast fault coverage estimation of sequential tests using entropy measurements. - Michael S. Hsiao; Sarmad Tanwir (VTS, 2018)

EASE: Enabling Hardware Assertion Synthesis from English. - Rahul Krishnamurthy; Michael S. Hsiao (RuleML+RR, 2019)

Controlled Natural Language Framework for Generating Assertions from Hardware Specifications. - Rahul Krishnamurthy; Michael S. Hsiao (ICSC, 2019)

Breaking Down High-Level Robot Path-Finding Abstractions in Natural Language Programming. - Yue Zhan; Michael S. Hsiao (AI*IA, 2020)

Transforming Natural Language Specifications to Logical Forms for Hardware Verification. - Rahul Krishnamurthy; Michael S. Hsiao (ICCD, 2020)

Automated Assertion Generation from Natural Language Specifications. - Steven J. Frederiksen; John Aromando; Michael S. Hsiao (ITC, 2020)

Formal Validation for Natural Language Programming using Hierarchical Finite State Automata. - Yue Zhan; Michael S. Hsiao (ICAART (1), 2021)

Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language Specifications. - Aditi; Michael S. Hsiao (ATS, 2022)

Automated Suggestions Framework for Processing Hardware Specifications Written in English. - Rahul Krishnamurthy; Michael S. Hsiao (FDL, 2022)

A Hybrid Approach for Automatic Feedback Generation in Natural Language Programming. - Yue Zhan; Michael S. Hsiao (TransAI, 2022)

Validatable Generation of System Verilog Assertions from Natural Language Specifications. - Aditi; Michael S. Hsiao (TransAI, 2023)