A New Reconfigurable Architecture for Single Cycle Context Switching. - Markus Hütter; Holger Bock; Michael Scheppler (IPDPS, 2003)

Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. - Francisco-Javier Veredas; Michael Scheppler; Will Moffat; Bingfeng Mei (FPL, 2005)

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. - Francisco-Javier Veredas; Michael Scheppler; Hans-Jörg Pfleiderer (DATE Designers' Forum, 2006)

LUT-based MPGAs for fast turnaround time conversion flow. - Francisco-Javier Veredas; Michael Scheppler; Bumei Zhai; Hans-Jörg Pfleiderer (ISCAS, 2006)

Regular Routing Architecture for a LUT-based MPGA. - Francisco-Javier Veredas; Michael Scheppler; Bumei Zhai; Hans-Jörg Pfleiderer (ISVLSI, 2006)

Non-Volatile Memories for Removable Media. - Rino Micheloni; Massimiliano Picca; Stefano Amato; Helmut Schwalm; Michael Scheppler; Stefano Commodaro (Proc. IEEE, 2009)