HPS, a new microarchitecture: rationale and introduction. - Yale N. Patt; Wen-mei W. Hwu; Michael Shebanow (MICRO, 1985)

Critical issues regarding HPS, a high performance microarchitecture. - Yale N. Patt; Stephen W. Melvin; Wen-mei W. Hwu; Michael Shebanow (MICRO, 1985)

Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. - Yale N. Patt; Wen-mei W. Hwu; Stephen W. Melvin; Michael Shebanow; Chein Chen; Jiajuin Wei (COMPCON, 1986)

Run-time generation of HPS microinstructions from a VAX instruction stream. - Yale N. Patt; Stephen W. Melvin; Wen-mei W. Hwu; Michael Shebanow; Chein Chen (MICRO, 1986)

On tuning the microarchitecture of an HPS implementation of the VAX. - James E. Wilson; Stephen W. Melvin; Michael Shebanow; Wen-mei W. Hwu; Yale N. Patt (MICRO, 1987)

Aquarius. - Alvin M. Despain; Yale N. Patt; Vason P. Srini; Philip Bitar; William R. Bush; C. Chien; Wayne Citrin; Barry Fagin; Wenwei Hwu; Stephen W. Melvin; Rick McGeer; Ashok Singhal; et al. (SIGARCH Comput. Archit. News, 1987)

Hardware support for large atomic units in dynamically scheduled machines. - Stephen W. Melvin; Michael Shebanow; Yale N. Patt (MICRO, 1988)

Single Instruction Stream Parallelism is Greater Than Two. - Michael Butler; Tse-Yu Yeh; Yale N. Patt; Mitch Alsup; Hunter Scales; Michael Shebanow (ISCA, 1991)

Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. - Mike Simone; A. Essen; A. Ike; A. Krishnamoorthy; Tak Maruyama; Niteen Patkar; M. Ramaswami; Michael Shebanow; V. Thirumalaiswamy; DeForest Tovey (ISCA, 1995)

Pervasive massively multithreaded GPU processors. - Michael Shebanow (Conf. Computing Frontiers, 2009)

Improving GPU performance via large warps and two-level warp scheduling. - Veynu Narasiman; Michael Shebanow; Chang Joo Lee; Rustam Miftakhutdinov; Onur Mutlu; Yale N. Patt (MICRO, 2011)

Peta Thread Computing [Keynote I]. - Michael Shebanow (ISPASS, 2013)

VBTC: GPU-Friendly Variable Block Size Texture Encoding. - Pavel Krajcevski; Abhinav Golas; K. Ramani; Michael Shebanow; Dinesh Manocha (Comput. Graph. Forum, 2016)

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. - Onur Mutlu; Rich Belgard; Thomas R. Gross; Norman P. Jouppi; John L. Hennessy; Steven A. Przybylski; Chris Rowen; Yale N. Patt; Wen-mei W. Hwu; Stephen W. Melvin; Michael Shebanow; Tse-Yu Yeh; et al. (IEEE Micro, 2016)