Minimizing the number of process corner simulations during design verification. - Michael Shoniker; Bruce F. Cockburn; Jie Han 001; Witold Pedrycz (DATE, 2015)

Automatic Selection of Process Corner Simulations for Faster Design Verification. - Michael Shoniker; Oleg Oleynikov; Bruce F. Cockburn; Jie Han 001; Manish Rana; Witold Pedrycz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)