40-Gb/s circuits built from a 120-GHz fT SiGe technology. - Greg G. Freeman; Mounir Meghelli; Young Kwark; Steven Zier; Alexander V. Rylyakov; Michael Sorna; Todd Tanji; Oswin M. Schreiber; Keith Walter; Jae-Sung Rieh; Basanth Jagannathan; Alvin J. Joseph; et al. (IEEE J. Solid State Circuits, 2002)

SiGe BiCMOS integrated circuits for high-speed serial communication links. - Daniel J. Friedman; Mounir Meghelli; Benjamin D. Parker; Jungwook Yang; Herschel A. Ainspan; Alexander V. Rylyakov; Young Hoon Kwark; Mark B. Ritter; Lei Shan; Steven J. Zier; Michael Sorna; Mehmet Soyuer (IBM J. Res. Dev., 2003)

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. - Mounir Meghelli; Alexander V. Rylyakov; Steven Zier; Michael Sorna; Daniel J. Friedman (IEEE J. Solid State Circuits, 2003)

10+ Gb/s 90nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (CICC, 2004)

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. - Troy J. Beukema; Michael Sorna; Karl Selander; Steven Zier; Brian L. Ji; Phil Murfet; James Mason; Woogeun Rhee; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes (IEEE J. Solid State Circuits, 2005)

10+ gb/s 90-nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (IEEE J. Solid State Circuits, 2005)

Root cause identification of an hard-to-find on-chip power supply coupling fail. - Franco Stellari; Thomas Cowell; Peilin Song; Michael Sorna; Zeynep Toprak Deniz; John F. Bulzacchelli; Nandita A. Mitra (ITC, 2012)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. - Gautam Reddy Gangasani; D. Hanson; Daniel W. Storaska; H. H. Xu; M. Kelly; M. Shannon; Michael Sorna; Michael Wielgos; P. B. Ramakrishna; S. Shi; S. Parker; U. K. Shukla; et al. (ISSCC, 2022)

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. - Gautam R. Gangasani; A. Mostafa; A. Singh; Daniel W. Storaska; D. Prabakaran; K. Mohammad; Matthew Baecher; M. Shannon; Michael Sorna; Michael Wielgos; P. Jenkins; P. B. Ramakrishna; et al. (VLSI Technology and Circuits, 2024)