Bounds for BEM Capacitance Extraction. - Michael W. Beattie; Lawrence T. Pileggi (DAC, 1997)

IC Analyses Including Extracted Inductance Models. - Michael W. Beattie; Lawrence T. Pileggi (DAC, 1999)

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. - Michael W. Beattie; Lawrence T. Pileggi (ICCAD, 1999)

Error bounds for capacitance extraction via window techniques. - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Hierarchical Interconnect Circuit Models. - Michael W. Beattie; Satrajit Gupta; Lawrence T. Pileggi (ICCAD, 2000)

Inductance 101: Modeling and Extraction. - Michael W. Beattie; Lawrence T. Pileggi (DAC, 2001)

Modeling Magnetic Coupling for On-Chip Interconnect. - Michael W. Beattie; Lawrence T. Pileggi (DAC, 2001)

Efficient inductance extraction via windowing. - Michael W. Beattie; Lawrence T. Pileggi (DATE, 2001)

Equipotential shells for efficient inductance extraction. - Michael W. Beattie; Byron Krauter; Lale Alatan; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

On the efficacy of simplified 2D on-chip inductance models. - Tao Lin; Michael W. Beattie; Lawrence T. Pileggi (DAC, 2002)

On-Chip Inductance Models: 3D or Not 3D? - Tao Lin; Michael W. Beattie; Lawrence T. Pileggi (DATE, 2002)

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. - Hui Zheng; Lawrence T. Pileggi; Michael W. Beattie; Byron Krauter (DATE, 2002)

On-chip induction modeling: basics and advanced methods. - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Parasitics extraction with multipole refinement. - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Spatially distributed 3D circuit models. - Michael W. Beattie; Hui Zheng; Anirudh Devgan; Byron Krauter (DAC, 2005)