A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. - Gautam Reddy Gangasani; D. Hanson; Daniel W. Storaska; H. H. Xu; M. Kelly; M. Shannon; Michael Sorna; Michael Wielgos; P. B. Ramakrishna; S. Shi; S. Parker; U. K. Shukla; et al. (ISSCC, 2022)

A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology. - A. Chowdhury; J. Ma; Y. Li; J. Guo; X. Zhang; P. B. Ramakrishna; J. Gu; Y. Wang; L. Liang; U. K. Shukla; K. Mohammad; H. Yan; et al. (VLSI Technology and Circuits, 2024)

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. - Gautam R. Gangasani; A. Mostafa; A. Singh; Daniel W. Storaska; D. Prabakaran; K. Mohammad; Matthew Baecher; M. Shannon; Michael Sorna; Michael Wielgos; P. Jenkins; P. B. Ramakrishna; et al. (VLSI Technology and Circuits, 2024)