Symbolic inner loop parallelisation for massively parallel processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (MEMOCODE, 2014)

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. - Vahid Lari; Alexandru Tanase; Jürgen Teich; Michael Witterauf; Faramarz Khosravi; Frank Hannig; Brett H. Meyer (AHS, 2015)

Adaptive fault tolerance through invasive computing. - Michael Witterauf; Alexandru Tanase; Jürgen Teich; Vahid Lari; Andreas Zwinkau; Gregor Snelting (AHS, 2015)

On-demand fault-tolerant loop processing on massively parallel processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig; Vahid Lari (ASAP, 2015)

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (MEMOCODE, 2015)

Techniques for on-demand structural redundancy for massively parallel processor arrays. - Vahid Lari; Jürgen Teich; Alexandru Tanase; Michael Witterauf; Faramarz Khosravi; Brett H. Meyer (J. Syst. Archit., 2015)

Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. - Michael Witterauf; Alexandru Tanase; Frank Hannig; Jürgen Teich (ASAP, 2016)

Providing fault tolerance through invasive computing. - Vahid Lari; Andreas Weichslgartner; Alexandru Tanase; Michael Witterauf; Faramarz Khosravi; Jürgen Teich; Jan Heißwolf; Stephanie Friederich; Jürgen Becker 001 (it Inf. Technol., 2016)

Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. - Michael Witterauf; Frank Hannig; Jürgen Teich (RSP, 2017)

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. - Éricles Sousa; Michael Witterauf; Marcel Brand; Alexandru Tanase; Frank Hannig; Jürgen Teich (ASAP, 2018)

Run-time Requirement Enforcement for Loop Programs on Processor Arrays. - Michael Witterauf; Jürgen Teich (MEMOCODE, 2018)

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. - Alexandru Tanase; Michael Witterauf; Jürgen Teich; Frank Hannig (ACM Trans. Embed. Comput. Syst., 2018)

Anytime instructions for programmable accuracy floating-point arithmetic. - Marcel Brand; Michael Witterauf; Frank Hannig; Jürgen Teich (CF, 2019)

Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. - Michael Witterauf; Frank Hannig; Jürgen Teich (MEMOCODE, 2019)

Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. - Christian Heidorn; Michael Witterauf; Frank Hannig; Jürgen Teich (J. Comput., 2019)

Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. - Marcel Brand; Michael Witterauf; Alberto Bosio; Jürgen Teich (ASAP, 2020)

Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. - Dominik Walter; Michael Witterauf; Jürgen Teich (MEMOCODE, 2020)

Aarith: an arbitrary precision number library. - Oliver Keszöcze; Marcel Brand; Michael Witterauf; Christian Heidorn; Jürgen Teich (SAC, 2021)

*-Predictable MPSoC execution of real-time control applications using invasive computing. - Marcel Brand; Michael Witterauf; Éricles Sousa; Alexandru Tanase; Frank Hannig; Jürgen Teich (Concurr. Comput. Pract. Exp., 2021)

Symbolic Loop Compilation for Tightly Coupled Processor Arrays. - Michael Witterauf; Dominik Walter; Frank Hannig; Jürgen Teich (ACM Trans. Embed. Comput. Syst., 2021)

A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays. - Michael Witterauf (2021)

ALPACA: An Accelerator Chip for Nested Loop Programs. - Dominik Walter; Marcel Brand; Christian Heidorn; Michael Witterauf; Frank Hannig; Jürgen Teich (ISCAS, 2024)