Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. - Jason Cong; Michail Romesis (DAC, 2001)

Microarchitecture evaluation with physical planning. - Jason Cong; Ashok Jagannathan; Glenn Reinman; Michail Romesis (DAC, 2003)

Optimality and Stability Study of Timing-Driven Placement Algorithms. - Jason Cong; Michail Romesis; Min Xie 004 (ICCAD, 2003)

Optimality, scalability and stability study of partitioning and placement algorithms. - Jason Cong; Michail Romesis; Min Xie 004 (ISPD, 2003)

An area-optimality study of floorplanning. - Jason Cong; Gabriele Nataneli; Michail Romesis; Joseph R. Shinnerl (ISPD, 2004)

Optimality and scalability study of existing placement algorithms. - Chin-Chih Chang; Jason Cong; Michail Romesis; Min Xie 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Microarchitecture evaluation with floorplanning and interconnect pipelining. - Ashok Jagannathan; Hannah Honghua Yang; Kris Konigsfeld; Dan Milliron; Mosur Mohan; Michail Romesis; Glenn Reinman; Jason Cong (ASP-DAC, 2005)

Robust mixed-size placement under tight white-space constraints. - Jason Cong; Michail Romesis; Joseph R. Shinnerl (ICCAD, 2005)

mPL6: a robust multilevel mixed-size placement engine. - Tony F. Chan; Jason Cong; Michail Romesis; Joseph R. Shinnerl; Kenton Sze; Min Xie 004 (ISPD, 2005)

Fast floorplanning by look-ahead enabled recursive bipartitioning. - Jason Cong; Michail Romesis; Joseph R. Shinnerl (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Locality and Utilization in Placement Suboptimality. - Jason Cong; Michalis Romesis; Joseph R. Shinnerl; Kenton Sze; Min Xie 004 (Modern Circuit Placement, 2007)

Locality and Utilization in Placement Suboptimality. - Jason Cong; Michalis Romesis; Joseph R. Shinnerl; Kenton Sze; Min Xie 004 (CoRR, 2023)