An Improved Architecture of a Hardware Accelerator for Factoring Integers with Elliptic Curve Method. - Michal Andrzejczak (FedCSIS, 2018)

The Low-Area FPGA Design for the Post-Quantum Cryptography Proposal Round5. - Michal Andrzejczak (FedCSIS, 2019)

Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign. - Viet Ba Dang; Farnoud Farahmand; Michal Andrzejczak; Kris Gaj (FPT, 2019)

Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5. - Michal Andrzejczak; Farnoud Farahmand; Kris Gaj (ReConFig, 2019)

Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches. - Viet Ba Dang; Farnoud Farahmand; Michal Andrzejczak; Kamyar Mohajerani; Duc Tri Nguyen; Kris Gaj (IACR Cryptol. ePrint Arch., 2020)

A Multiplatform Parallel Approach for Lattice Sieving Algorithms. - Michal Andrzejczak; Kris Gaj (IACR Cryptol. ePrint Arch., 2021)

Quantum-Resilient IoT: Integrating Hardware-Based Post-Quantum Cryptography for Robust Device Security. - Stephan Spitz; Alexander Lawall; Michal Andrzejczak (ICISSP (2), 2025)