Packet Classification with Limited Memory Resources. - Michal Kekely; Jan Korenek (DSD, 2017)

Line rate programmable packet processing in 100Gb networks. - Pavel Benácek; Viktor Pus; Jan Korenek; Michal Kekely (FPL, 2017)

Mapping of P4 match action tables to FPGA. - Michal Kekely; Jan Korenek (FPL, 2017)

200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards. - Zdenek Martinasek; Jan Hajny; David Smekal; Lukas Malina; Denis Matousek; Michal Kekely; Nele Mentens (ASHES@CCS, 2018)

Memory Aware Packet Matching Architecture for High-Speed Networks. - Michal Kekely; Lukas Kekely; Jan Korenek (DSD, 2018)

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. - Jakub Cabal; Pavel Benácek; Lukas Kekely; Michal Kekely; Viktor Pus; Jan Korenek (FPGA, 2018)

Pipelined ALU for effective external memory access in FPGA. - Tomás Benes; Michal Kekely; Karel Hynek; Tomás Cejka (DSD, 2020)

General memory efficient packet matching FPGA architecture for future high-speed networks. - Michal Kekely; Lukás Kekely; Jan Korenek (Microprocess. Microsystems, 2020)

Optimizing Packet Classification on FPGA. - Michal Kekely; Jan Korenek (DDECS, 2023)

Mapování zpracování paketů popsaného v jazyce P4 do technologie FPGA ; Mapping of packet processing from P4 Language to FPGA Technology. - Michal Kekely (2024)