A knowledge-based software development environment for scientific model-building. - Richard M. Keller; Michal Rimon (KBSE, 1992)

A knowledge-based prototyping environment for construction of scientific modeling software. - Richard M. Keller; Michal Rimon; Aseem Das (Autom. Softw. Eng., 1994)

Improving test quality through resource reallocation. - Allon Adir; Eitan Marcus; Michal Rimon; Amir Voskoboynik (HLDVT, 2001)

Industrial experience with test generation languages for processor verification. - Michael L. Behm; John M. Ludden; Yossi Lichtenstein; Michal Rimon; Michael Vinov (DAC, 2004)

Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. - Allon Adir; Eli Almog; Laurent Fournier; Eitan Marcus; Michal Rimon; Michael Vinov; Avi Ziv (IEEE Des. Test Comput., 2004)

VLIW: a case study of parallelism verification. - Allon Adir; Yaron Arbetman; Bella Dubrov; Yossi Lichtenstein; Michal Rimon; Michael Vinov; Massimo A. Calligaro; Andrew Cofler; Gabriel Duffy (DAC, 2005)

Addressing Test Generation Challenges for Configurable Processor Verification. - Michal Rimon; Yossi Lichtenstein; Allon Adir; Itai Jaeger; Michael Vinov; S. Johnson; D. Jani (HLDVT, 2006)

Constraint-Based Random Stimuli Generation for Hardware Verification. - Yehuda Naveh; Michal Rimon; Itai Jaeger; Yoav Katz; Michael Vinov; Eitan Marcus; Gil Shurek (AI Mag., 2007)

Advances in Simultaneous Multithreading Testcase Generation Methods. - John M. Ludden; Michal Rimon; Bryan G. Hickerson; Allon Adir (Haifa Verification Conference, 2010)

Ontology-Based Tools in the Service of Hardware Verification. - Eyal Bin; Alaa Ghanayim; Karen Holtz; Eitan Marcus; Ronny Morad; Ofer Peled; Michal Rimon; Gil Shurek; Elena Tsanko (SEKE, 2010)

Learning microarchitectural behaviors to improve stimuli generation quality. - Yoav Katz; Michal Rimon; Avi Ziv; Gai Shaked (DAC, 2011)

Generating instruction streams using abstract CSP. - Yoav Katz; Michal Rimon; Avi Ziv (DATE, 2012)

A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs. - Yoav Katz; Michal Rimon; Avi Ziv (Haifa Verification Conference, 2012)

Solutions to IBM POWER8 verification challenges. - Klaus-Dieter Schubert; John M. Ludden; Salma Ayub; J. Behrend; Bishop Brock; Fady Copty; S. M. German; Oz Hershkovitz; H. Horbach; Jonathan R. Jackson; K. Keuerleber; J. Koesters; et al. (IBM J. Res. Dev., 2015)